Dielectric Interconnect Research Articles

Integration of Self-Assembled Monolayers for Cobalt/Porous Low-k Interconnects

The integration of self-assembled monolayers (SAM) into cobalt (Co)/porous low-dielectric-constant (low-k) dielectric interconnects is studied in terms of electrical characteristics and reliability in this work. Experimental results indicated that SAM derived from 3-aminopropyltrimethoxysilane (APTMS) improved breakdown field, time-dependent dielectric breakdown, and adhesion for Co/porous low-k integrated interconnects. However, the improvement magnitude was not large as compared to SAM in the Cu/porous low-k integration. Therefore, the integration of SAM into Co/porous low-k interconnects has a positive effect; however, in order to further promote the efficiency of SAM for Co/porous low-k interconnects, the option of precursors for the growth of SAM is required.

(Invited) Fan-out and Cu- Compatible Dielectric Processing of Low Temperature Polyimides for Next-Generation 3D Advanced IC Back End Applications

Fan-out (FO) wafer and panel level processing in advanced backend applications requires the curing of RDL (Redistribution Layers) or interconnect dielectrics at lower temperatures in order to manage stress and relevant warpage for multi-level or 3D processing. In addition, the need to transition to all-Cu interconnect has resulted in a temperature limit of 230°C for large numbers of end products. Most of these products employ the advanced packaging capabilities of heterogeneous and 3D integration, 3D stacking and system-in-package (SIP) technology, whereby a variety of chiplets and other components are stacked, delivering high compute density and high performance at low cost. Multi-layer RDLs are used to connect these dissimilar chips on organic, glass, silicon or fan-out substrates. Consequently, process technology for polyimide, photo imageable dielectric (PID) and photo sensitive polyimide (PSPI) must now enable a faster cure at lower temperatures to achieve lower stress, while also delivering better film properties.In this talk, the physical, mechanical, thermal, and electrical properties of different types of polyimide materials will be discussed as a function of different process parameters, under atmospheric and vacuum process conditions. The talk references a study in which a variety of low temperature RDL polyimides such as HD-7110, Asahi BL-301 and Fuji-LTC9320 were processed at a temperature of less than 230°C, and then compared to conventional polyimide HD-4100. Vacuum cure even at lower temperatures resulted in higher thermal stability, lower outgassing, and better thermal properties. In electrical characterization, vacuum cure showed better dielectric strength as well as a lower dissipation factor. These results are consistent with the assumption that cure under vacuum reduces the amount of volatile and volatilizable material remaining in the film after the cure process.The use of sub-atmospheric curing or annealing technology at low temperature improved both the quality and the performance of the cured polyimide films for RDL applications. These results are relevant to the multi-level metallization process of Fan Out Wafer Level Packaging (FOWLP) and Fan Out Panel Level Packaging (FOPLP), and therefore to 3D stack integration.

Vapor-deposited zeolitic imidazolate frameworks as gap-filling ultra-low-k dielectrics

The performance of modern chips is strongly related to the multi-layer interconnect structure that interfaces the semiconductor layer with the outside world. The resulting demand to continuously reduce the k-value of the dielectric in these interconnects creates multiple integration challenges and encourages the search for novel materials. Here we report a strategy for the integration of metal-organic frameworks (MOFs) as gap-filling low-k dielectrics in advanced on-chip interconnects. The method relies on the selective conversion of purpose-grown or native metal-oxide films on the metal interconnect lines into MOFs by exposure to organic linker vapor. The proposed strategy is validated for thin films of the zeolitic imidazolate frameworks ZIF-8 and ZIF-67, formed in 2-methylimidazole vapor from ALD ZnO and native CoOx, respectively. Both materials show a Young’s modulus and dielectric constant comparable to state-of-the-art porous organosilica dielectrics. Moreover, the fast nucleation and volume expansion accompanying the oxide-to-MOF conversion enable uniform growth and gap-filling of narrow trenches, as demonstrated for 45 nm half-pitch fork-fork capacitors.

Future Dielectric Materials for CNT Interconnects - Possibilities and Challenges

Carbon nanotube (CNT) interconnects are emerging as the ultimate choice for next generation ultra large scale integrated (ULSI) circuits. Significant progress in precise growth of aligned CNTs and integration of multiwalled CNT interconnects into a test chip make them promising candidates for future nanoelectronic chips. Tremendous research efforts were made on silicon based ultra-low-k dielectrics for Cu interconnects, but, the most recent advancements in polymer based composites as dielectric materials open up fresh challenges in the use of low-k dielectrics for CNT interconnects. This paper reviews the emerging polymer composites like Boron Nitride Nanotubes, Graphene/Polyimide composites, Metal Organic Frameworks and small diameter CNTs. Many reviews are already exists on the synthesis, fabrication, dielectric, mechanical, chemical and thermal properties of these materials. In this review, we have explained the specific properties of these materials and the necessities for integrating them into CNT interconnects to meet the requirements of future IC designers.Keywords: low-k dielectric materials, ultra low-k dielectrics, carbon nanotubes, interconnects, dielectric constant,

Extreme-low k porous pSiCOH dielectrics prepared by PECVD

A novel extreme low-k (ELK) porous SiCOH (pSiCOH) dielectric has been developed by adding a third carbosilane precursor to the diethoxymethylsilane and bicycloheptadiene precursors used in the plasma enhanced chemical vapor deposition fabrication process of ultralow-k pSiCOH interconnect dielectrics. By adjusting the plasma parameters, the dielectric constant (k) has been lowered to k < 2.1. The k value of the ELK dielectric has been further reduced to 1.8 by extracting the porogen from the as-deposited films before subjecting them to ultraviolet cure using hydrogen radicals. It was found that the carbon concentration and the porosity of the ELK film can be tuned with different porogen extraction times in order to control the final k value of the dielectric.

Fabrication method for annular/shielded copper interconnects

This study outlines a method for fabricating annular/shielded on chip copper interconnects. Traditional damascene copper wires only require one diffusion barrier to prevent copper migration into dielectrics for trench style interconnects. However, for annular or shielded interconnects, an additional diffusion/oxidation barrier is required to protect the integrity of the copper especially on the trench sidewalls. Two methods are explored in this study to create the second barrier that includes materials such as tantalum nitride and silicon nitride (SiN). The experimental results are analysed using scanning electron microscopy (SEM) and high frequency electrical measurements to characterise the effectiveness of each respective technique. The results demonstrate the feasibility of creating annular/shielded copper interconnects using standard damascene processing techniques to maintain lower costs of process development. Furthermore, the results conclude the SiN based barrier effectively prevents oxidation of copper as verified with both SEM and electrical data. The development of this knowledge will aid in advancing back end interconnect technology to help solve the data bottleneck issue currently challenging the semiconductor industry.

Heterogeneous Integration for Performance and Scaling

Moore’s law has so far relied on the aggressive scaling of CMOS silicon minimum features of over $1000\times $ for over four decades, and recently, on the adoption of innovative features, such as Cu interconnects, low- $k$ dielectrics for interconnects, strained channels, and high- $k$ materials for gate dielectrics, resulting in a better power performance, cost per function, and density every generation. This has spawned a vibrant system-on-chip (SoC) approach, where progressively more function has been integrated on a single die. The integration of multiple dies on packages and boards has, however, scaled only modestly by a factor of three to five times. In this paper, we show that with the apparent slowing down of semiconductor scaling and the advent of the Internet of Things, there is a focus on heterogeneous integration and system-level scaling. Packaging is undergoing a transformation that focuses on overall system performance and cost rather than on individual components. We propose ways in which this transformation can evolve to provide a significant value at the system level while providing a significantly lower barrier to entry compared with a chip-based SoC approach that is currently used. This transformation is already under way with 3-D stacking of dies and will evolve to make heterogeneous integration the backbone of sustaining Moore’s law in the years ahead.

Preparation and unique dielectric properties of nanoporous materials with well-controlled closed-nanopores.

Although general porous materials have a low dielectric constant, their uncontrollable opened porous structure results in high dielectric loss and poor barrier properties, thus limiting their application as interconnect dielectrics. In this study, polymeric nanoporous materials with well-controlled closed pores were prepared by incorporating polystyrene (PS) hollow nanoparticles into polyethylene (PE/HoPS). SEM images suggested a closed porous structure for PE/HoPS. In order to show the effect of the porous structure on dielectric properties, nanoporous materials with an opened or uncontrollable porous structure were prepared by etching SiO2/PE or PE/PS@SiO2 composites. PE/HoPSs composites showed an apparently lower dielectric constant and loss compared with the opened porous PE, demonstrating the advantages of a closed porous structure upon enhancing low-dielectric performance. The low dielectric performance of the PE/HoPS composites is linked with high water resistance owing to their closed porous characteristics. When incorporating 15.3 wt% HoPS (porosity: ∼6.9%), the dielectric constant reached 2.08. This value is lower than that calculated from the serial model. Our work revealed that the incorporation of HoPS not only reduces the porosity, but also alters the intrinsic properties of PE, as a result, leading to a greatly reduced dielectric constant.

Synthesis and applications of two-dimensional hexagonal boron nitride in electronics manufacturing

In similarity to graphene, two-dimensional (2D) hexagonal boron nitride (hBN) has some remarkable properties, such as mechanical robustness and high thermal conductivity. In addition, hBN has superb chemical stability and it is electrically insulating. 2D hBN has been considered a promising material for many applications in electronics, including 2D hBN based substrates, gate dielectrics for graphene transistors and interconnects, and electronic packaging insulators. This paper reviews the synthesis, transfer and fabrication of 2D hBN films, hBN based composites and hBN-based van der Waals heterostructures. In particular, this review focuses on applications in manufacturing electronic devices where the insulating and thermal properties of hBN can potentially be exploited. 2D hBN and related composite systems are emerging as new and industrially important materials, which could address many challenges in future complex electronics devices and systems.

(Invited) Challenges to Nano-Scale Device World

The historic trend in micro/nano-electronics these last 40 years has been to increase both speed and density by scaling down the electronic devices, together with reduced energy dissipation per binary transition, and to develop many novel functionalities for future electronic systems. We are facing today dramatic challenges for More Moore and More than more applications: substantial increase of energy consumption and heating which can jeopardize future IC integration and performance, reduced performance due to limitation in traditional high conductivity metal/low k dielectric interconnects, limit of optical lithography, heterogeneous integration of new functionalities for futures nanosystems, etc. [1-16]. Therefore many breakthroughs, disruptive technologies, novel materials, and innovative devices are needed in the next two decades. With respect to the substantial reduction of the static and dynamic power of future high performance/ultra low power terascale integration and autonomous nanosystems, new materials and novel device architectures are mandatory for ultimate CMOS and beyond-CMOS eras, as well as new circuit design techniques, architectures and embedded softwares. Alternative memories, especially PCRAM, RRAM or MRAM will be useful for pushing the limit of integration and performance beyond to those afforded by present Non-Volatile, DRAM and SRAM memories. In the interconnect area, optical and RF interconnects, carbon or other 2D materials can overcome the present limitations of copper interconnects. Concerning ultimate processing technologies, EUV lithography, immersion multiple patterning, multi ebeam maskless or imprint lithography, as well as self-assembly of nanodevices could be used for different applications. Future autonomous nanosystems will also need the development of nanoscale high performance novel functionalities, which could be integrated on CMOS platforms. In this respect, nanostructures and nanodevices, especially nanowires, are of great interest for instance for improving the sensitivity, resolution, selectivity, energy consumption and response time of nanosensors, and for solar, mechanical and thermal energy harvesting. Parallel or sequential processes could be used for the integration of these future high performance sustainable, secure, ubiquitous and pervasive systems, which will be of high added value for many applications in the field of detection and communication of health problems, environment quality and security, secure transport, building and industrial monitoring, entertainment, education, etc. The talk will focus on the main trends, challenges, limits and possible solutions for future high performance and ultralow power nanoscale devices in the CMOS and Beyond CMOS arena, including ultra-thin films, multi-gates, nanowires and small slope switches.

Mechanical property changes in porous low-k dielectric thin films during processing

The design of future generations of Cu-low-k dielectric interconnects with reduced electronic crosstalk often requires engineering materials with an optimal trade off between their dielectric constant and elastic modulus. This is because the benefits associated with the reduction of the dielectric constant by increasing the porosity of materials, for example, can adversely affect their mechanical integrity during processing. By using load-dependent contact-resonance atomic force microscopy, the changes in the elastic modulus of low-k dielectric materials due to processing were accurately measured. These changes were linked to alterations sustained by the structure of low-k dielectric films during processing. A two-phase model was used for quantitative assessments of the elastic modulus changes undergone by the organosilicate skeleton of the structure of porous and pore-filled dielectrics.

Progress in the development and understanding of advanced low k and ultralow k dielectrics for very large-scale integrated interconnects—State of the art

The improved performance of the semiconductor microprocessors was achieved for several decades by continuous scaling of the device dimensions while using the same materials for all device generations. At the 0.25 μm technology node, the interconnect of the integrated circuit (IC) became the bottleneck to the improvement of IC performance. One solution was introduction of new materials to reduce the interconnect resistance-capacitance. After the replacement of Al with Cu in 1997, the inter- and intralevel dielectric insulator of the interconnect (ILD), SiO2, was replaced about 7 years later with the low dielectric constant (low-k) SiCOH at the 90 nm node. The subsequent scaling of the devices required the development of ultralow-k porous pSiCOH to maintain the capacitance of the interconnect as low as possible. The composition and porosity of pSiCOH dielectrics affected, among others, the resistance of the dielectrics to damage during integration processing and reduced their mechanical strength, thereby affecting the reliability of the VLSI microprocessor. New ILDs had to be developed to overcome such problems and enable the fabrication of reliable high performance devices. The capacitance of the interconnect is also affected by the dielectric caps separating the Cu conductor from the ILD. This effect has increasing impact as interconnect dimensions shrink further with each technology node. New caps with lower k values and smaller thickness have been developed to reduce the impact of the caps to the capacitance of the interconnect and enable fabrication of devices of high reliability. This paper reviews the development of advanced ultralow-k (ULK) ILD dielectrics and caps with reduced capacitance contributions and presents the state of the art of these interconnect dielectrics.

Roles of plasma-generated vacuum-ultraviolet photons and oxygen radicals in damaging nanoporous low-k films

One important class of low-k materials used as interconnect dielectrics employs methyl groups added to nanoporous SiO2 matrices. These carbon-doped oxide materials are known to be susceptible to damage from plasma species during various stages of plasma processing. Two key active species generated in O2 plasma are oxygen (O) radicals and vacuum-ultraviolet (VUV) photons. These species are known to cause carbon loss, resulting in damaging increases in dielectric constant throughout the film. However, the mechanisms through which this damage is incurred are poorly understood. By capping the substrate in different ways during plasma exposure, it is possible to expose films to either photons alone or O atoms alone. The authors report measurements of damage induced by VUV photons only, O radicals only, and the combination of O radicals and photons. Through HF stripping, they note that carbon extraction from photons and from radicals yields different outcomes; the profile of carbon concentration within the modified region is different for each case. Damage from photons alone can be modeled and model predictions are in good agreement with measurements. Damage from O atoms alone can only be modeled if it is assumed that the near-surface region has a significantly reduced diffusivity compared to the bulk of the film. Experiment and model agree that both photons alone and O radicals alone damage the material by removing carbon. When radicals and photons are present simultaneously during plasma exposure, however, more C removal appears to be occurring in the model than experimentally observed. Remarkably, if only radicals are exposed to the film after short (10–30 s) plasma exposures, very little additional damage is incurred during this radical-only exposure. The most straightforward interpretation of these results appears to be that photons combine synergistically with radicals in the pores to narrow the pores, thereby reducing film diffusivity in the C-poor, plasma-damaged regions.

Formation of Porous Low-K Dielectric Interconnect Structure on Advanced Dielectric-Reactive Ion Etcher

Porous low-k dielectrics have been extensively integrated into back-end-of-line (BEOL) for its significant improvement of chip resistance-capacitance (RC) delay performance. However, Metal hard-mask (MHM) has to be introduced to reduce the low-k damage from radicals and photons during plasma strip. We investigated the formation of porous low-k dielectric interconnect structure on advanced dielectric reactor ion etcher (AD-RIE) of AMEC (Advanced Micro-fabrication Equipment Company) from the point of view of etch profile, wafer acceptance test (WAT), RC delay performance and reliability (RE). Scanning electron microscope (SEM) results exhibit the desired etch profiles for both trench and via. The WAT electrical results, RC delay and RE performances can be well improved by etch profile control. In brief, all of these demonstrate AD-RIE is capable of delivering the qualified porous low-k dielectric structure as main-stream etchers did.

All-In-One Etch Scheme to the Fabrication of Metal Hard-Mask Based Cu/Ultra Low-K Interconnects

Due to the inherent limitation from overlay shift control, the punch-through scheme coupled with via CD shrink and the definition optimization of metal hard-mask open was proven to be the current-best choice and only feasible way for the enhancement of TDDB performance and gap-fill window of metal hard-mask based ultra low-k dielectric interconnects. The disadvantages of metal hard-mask based all-in-one etch include the potential defect from TixFy and the early copper exposure before liner removal step. The copper exposure time during all-in-one etch needs well controlled to avoid the via/trench bottom roughness and the inter-layer VBD. Stress migration (SM) also attracts special attention in metal hard-mask based process and its performance can be improved from the point of view of WET clean and post etch treatment (PET). RC (resistance/capacitance) curve can be also improved to target by means of PET.

Cu Single Damascene Integration of an Organic Nonporous Ultralow- $k$ Fluorocarbon Dielectric Deposited by Microwave-Excited Plasma-Enhanced CVD

An integration of an organic nonporous ultralow- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectric fluorocarbon ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> = 2.2) deposited by microwave-excited plasma-enhanced CVD into Cu single damascene interconnects is developed in this paper. The changing of the chemical structure of the fluorocarbon was found after dry etching, which resulted in the degradation of electrical properties during the postetching cleaning process. A nitrogen plasma treatment was applied as a postetching process to minimize damage introduction to the fluorocarbon in the following damascene fabrication processes, and a line-to-line leakage current was significantly improved without the variance of effective dielectric constant ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">eff</sub> = 2.5) in Cu lines. In a thermal stress test at 350 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C after Cu-interconnect fabrication, no degradation of the Cu line resistance and line-to-line capacitance was found, which indicated a sufficient thermal stability of the fluorocarbon film in Cu single damascene interconnects. Therefore, this robust organic nonporous fluorocarbon film is considered as one of the promising candidates of ultralow- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</i> dielectrics for high-performance Cu interconnects in the future.

Delayed mechanical failure of the under-bump interconnects by bump shearing

Packaging-induced stresses can cause mechanical failures of various forms in the Cu/low-k interconnects. Here we report a time-dependent failure mode of the interconnects underneath the copper pillar bump. Delayed catastrophic fracture is observed in the interconnect dielectrics when a sustained shear load is applied on the bump using a single bump shear setup. The time to failure is found to be highly sensitive to the load level and temperature, but not to the environmental humidity. However, moisture diffusion through intentionally broken moisture seal can accelerate the failure process. Quantitative analysis suggests the delayed failure can be well captured over a wide range of testing conditions by a model based on subcritical crack growth in the interconnect dielectrics.

Die singulation technologies for advanced packaging: A critical review

Die singulation, also known as wafer dicing, is reviewed in terms of the brief history, critical challenges, characterization of singulation quality, different singulation technologies and underlying mechanisms, and post-singulation die strength enhancement. Mechanical blade dicing has been the workhorse of die separation in the semiconductor manufacturing process. It faces growing challenges due to the adoption of copper/low-k dielectric interconnect structures, thin and ultra-thin wafers, die attach films, narrow dicing streets, and complex stacked structures on the dicing streets. Key dicing quality characteristics are chipping, delamination, kerf geometry, die side wall damage, die surface contamination, and die strength degradation. Various die singulation technologies have been developed to address these challenges and quality issues, including dicing by thinning, laser based approaches, laser and mechanical hybrid method, and plasma dicing. Die strength is a critical parameter for thin and ultra-thin dies. Post-dicing die strength enhancement is becoming the complement of most dicing technologies to achieve dies with high fracture strength. Plasma dicing has the potential to achieve much higher die strengths than all the other dicing approaches.

Understanding the Impact of Porosity and Pore Structure in Ultra Low Dielectric Constant Organosilicate Glasses

ABSTRACTRecently there have been a number of reports indicating concern relating to the effect of porosity, pore size distribution, and pore interconnectivity on the integration of highly porous ultra low-k organosilicate glasses (OSGs) as back-end-of-line (BEOL) interconnect dielectrics. In an effort to address these concerns a number of options to control the skeleton and pore structure of OSGs have been proposed, from adding alternative OSG precursors to alternative porogen precursors. In all these options there is a need to balance pore structure modification with critical film properties such as dielectric constant and mechanical strength. In this context, this paper examines porosity and its impact on film properties for highly porous ultra low dielectric constant films. A series of PDEMS® porous OSG films were deposited by plasma enchanced chemical vapor deposition (PECVD) from DEMS® precursor (diethoxymethylsilane) and porogen ATRP (alpha-terpenine). The percent porosity and pore interconnectivity of these films relative to the dielectric constant were measured by ellipsometric porosimetry (EP) and positron annihilation spectroscopy (PALS) respectively. Porosity and pore-size distribution for films deposited using several different species (structure former or porogen precursors) were examined using EP in an effort to understand the impact of the chemical nature of the precursor on pore morphology. Results from these depositions show that it is possible to deposit films with smaller pores using alternative structure formers (ASFs) with bulky organic groups, although there are tradeoffs with respect to other film characteristics. The addition of a separate porogen (ATRP) to the ASF lowered the dielectric constant and the addition of DEMS® precursor to the ASF/ATRP mix gave the films added structural integrity and mechanical strength. Such a fundamental understanding of structure-property relationships will help support successful integration of these porous OSG films.

Effect of Colloidal Silica as Abrasive on Low-k Dielectric Materials in Chemical Mechanical Planarization

With low-k dielectric materials taking the place of oxide dielectrics as the primary dielectric materials, the low-k dielectric materials and interconnection Cu metals during Chemical Mechanical Planarization (CMP) is becoming a critical surface quality issue as well. In this study, experiments are carefully designed and conducted to investigate the effects of colloidal silica under compared acidic slurry and self-prepared alkaline slurry on k value of low-k dielectric materials, and in both of the slurry, colloidal silica (20~30nm) was used as polishing abrasive. The results showed that k value of low-k dielectric materials both increased within a similar range (self-prepared alkaline slurry, 3.27~3.33; commercial acidic slurry, 3.26~3.32), however, the results showed a obviously different result from reference’s report.