Formation of Porous Low-K Dielectric Interconnect Structure on Advanced Dielectric-Reactive Ion Etcher

Abstract

Porous low-k dielectrics have been extensively integrated into back-end-of-line (BEOL) for its significant improvement of chip resistance-capacitance (RC) delay performance. However, Metal hard-mask (MHM) has to be introduced to reduce the low-k damage from radicals and photons during plasma strip. We investigated the formation of porous low-k dielectric interconnect structure on advanced dielectric reactor ion etcher (AD-RIE) of AMEC (Advanced Micro-fabrication Equipment Company) from the point of view of etch profile, wafer acceptance test (WAT), RC delay performance and reliability (RE). Scanning electron microscope (SEM) results exhibit the desired etch profiles for both trench and via. The WAT electrical results, RC delay and RE performances can be well improved by etch profile control. In brief, all of these demonstrate AD-RIE is capable of delivering the qualified porous low-k dielectric structure as main-stream etchers did.