Dielectric Integrity Research Articles

Electrical Studies on Parylene-C Columnar Microfibrous Thin Films

Columnar microfibrous thin films (μFTFs) of Parylene C are deposited on top of p-type Si substrate using physicochemical vapor deposition to form metal-insulator-semiconductor and metal-insulator-metal structures utilizing the Parylene-C μFTFs as the gate dielectric. The columnar μFTFs were characterized for their electrical properties and dielectric integrity using leakage-current and capacitance measurements at temperatures in the 200K - 500 K range and at frequencies in the range 1 kHz to 1 MHz. Observed variations in leakage current and capacitance were found to be consistent with transport mechanisms involving the Poole–Frenkel and Schottky emission mechanisms as well as carrier trapping/detrapping at interfacial traps.

Damage free integration of ultralow-k dielectrics by template replacement approach

Cu/low-k integration by conventional damascene approach is becoming increasingly difficult as critical dimensions scale down. An alternative integration scheme is studied based on the replacement of a sacrificial template by ultralow-k dielectric. A metal structure is first formed by patterning a template material. After template removal, a k = 2.31 spin-on type of porous low-k dielectric is deposited onto the patterned metal lines. The chemical and electrical properties of spin-on dielectrics are studied on blanket wafers, indicating that during hard bake, most porogen is removed within few minutes, but 120 min are required to achieve the lowest k-value. The effective dielectric constant of the gap-fill low-k is investigated on a 45 nm ½ pitch Meander-Fork structure, leading to keff below 2.4. The proposed approach solves the two major challenges in conventional Cu/low-k damascene integration approach: low-k plasma damage and metal penetration during barrier deposition on porous materials.

Electrical Studies on Parylene-C Columnar Microfibrous Thin Films

Future advances in solid-state device technology are dependent on innovations in multifunctional materials and novel deposition processes and, hence, a wide spectrum of new material compositions and morphologies are being explored. For this study, microfibrous thin films (µFTFs) of Parylene C [1,2] were deposited on top of p-type Si substrates using physicochemical vapor deposition in a PDS2010 Labcoater to form metal-insulator–semiconductor (MIS) and metal–insulator–metal (MIM) capacitor structures utilizing the Parylene-C µFTF as the gate dielectric. Each µFTF was deposited with a collimated vapor flux of Parylene-C monomers inclined at 60° to the substrate plane and had a thickness of about 100 µm. The Parylene-C µFTFs were characterized for electrical properties and dielectric integrity using leakage current, equivalent series resistance and reactance, capacitance measurements at temperatures ranging from –40 °C to 125 °C and frequencies ranging from 1 kHz to 1 MHz, as well as field-emission scanning electron microscopy. The observed variations in leakage current can be explained in terms of transport mechanisms involving thermionic emission and electron hopping. Capacitance and dielectric loss data were analyzed. We found that higher leakage current does not allow for a reliable estimation of the dielectric constant. [1] Pursel, S., Horn, M. W., Demirel, M. C., & Lakhtakia, A. (2005). Growth of sculptured polymer submicronwire assemblies by vapor deposition, Polymer, 46(23), 9544–9548. [2] Chindam, C., Wonderling, N. M., Lakhtakia, A., Awadelkarim, O. O., & Orfali, W. (2015). Microfiber inclination, crystallinity, and water wettability of microfibrous thin-film substrates of Parylene C in relation to the direction of the monomer vapor during fabrication, Applied Surface Science, 345(1), 145–155.

Investigation of amorphous RuMoC alloy films as a seedless diffusion barrier for Cu/p-SiOC:H ultralow-k dielectric integration

Ultrathin RuMoC amorphous films prepared by magnetron co-sputtering with Ru and MoC targets in a sandwiched scheme Si/p-SiOC:H/RuMoC/Cu were investigated as barrier in copper metallization. The evolution of final microstructure of RuMoC alloy films show sensitive correlation with the content of doped Mo and C elements and can be easily controlled by adjusting the sputtering power of the MoC target. There was no signal of interdiffusion between the Cu and SiOC:H layer in the sample of Cu/RuMoC/p-SiOC:H/Si, even annealing up to 500 °C. Very weak signal of oxygen have been confirmed in the RuMoC barrier layer both as-deposited and after being annealed, and a good performance on preventing oxygen diffusion has been proved. Leakage current and resistivity evaluations also reveal the excellent thermal reliability of this Si/p-SiOC:H/RuMoC/Cu film stack at the temperatures up to 500 °C, indicating its potential application in the advanced barrierless Cu metallization.

Low Dit HfO2/Al2O3/In0.53Ga0.47As gate stack achieved with plasma-enhanced atomic layer deposition

We developed Al2O3 and HfO2 plasma-enhanced atomic layer deposition (PEALD) processes as part of the integration of a new high-k/In0.53Ga0.47As gate stack. The Al2O3 featured a bandgap of 7.0eV and a k-value of 8.1, while the HfO2 presented a bandgap of 6.2eV and a k-value of 14.6. W/HfO2/Al2O3/n-In0.53Ga0.47As metal-oxide-semiconductor capacitors (MOSCAPs) were fabricated and different In0.53Ga0.47As surface preparations [HF or (NH4)2S] were tested. Both surface preparations revealed similar gate stack electrical performance. Capacitance–voltage (C–V) characteristics yielded very low frequency dispersion near accumulation (as low as 0.3% at Vg=1V). Low (<1012/cm2eV) density of interface traps (Dit) in the upper part of the In0.53Ga0.47As bandgap was also extracted from the high-low frequency C–V and conductance methods, confirming the suitability of PEALD for the integration of high-k dielectrics in n-channel In0.53Ga0.47As field effect transistors.

Structural reliability evaluation of low-k nanoporous dielectric interlayers integrated into microelectronic devices

Structural reliability assessment on the integration of low-k nanoporous dielectrics into a multilayer structure, involving capping, chemical mechanical polishing, post-cleaning, and thermal annealing processes, was successfully demonstrated in a nondestructive manner.

Probing the molecular structures of plasma-damaged and surface-repaired low-k dielectrics.

Fully understanding the effect and the molecular mechanisms of plasma damage and silylation repair on low dielectric constant (low-k) materials is essential to the design of low-k dielectrics with defined properties and the integration of low-k dielectrics into advanced interconnects of modern electronics. Here, analytical techniques including sum frequency generation vibrational spectroscopy (SFG), Fourier transform infrared spectroscopy (FTIR), contact angle goniometry (CA) and X-ray photoelectron spectroscopy (XPS) have been employed to provide a comprehensive characterization of the surface and bulk structure changes of poly(methyl)silsesquioxane (PMSQ) low-k thin films before and after O2 plasma treatment and silylation repair. O2 plasma treatment altered drastically both the molecular structures and water structures at the surfaces of the PMSQ film while no bulk structural change was detected. For example, ∼34% Si-CH3 groups were removed from the PMSQ surface, and the Si-CH3 groups at the film surface tilted toward the surface after the O2 plasma treatment. The oxidation by the O2 plasma made the PMSQ film surface more hydrophilic and thus enhanced the water adsorption at the film surface. Both strongly and weakly hydrogen bonded water were detected at the plasma-damaged film surface during exposure to water with the former being the dominate component. It is postulated that this enhancement of both chemisorbed and physisorbed water after the O2 plasma treatment leads to the degradation of low-k properties and reliability. The degradation of the PMSQ low-k film can be recovered by repairing the plasma-damaged surface using a silylation reaction. The silylation method, however, cannot fully recover the plasma induced damage at the PMSQ film surface as evidenced by the existence of hydrophilic groups, including C-O/C[double bond, length as m-dash]O and residual Si-OH groups. This work provides a molecular level picture on the surface structural changes of low-k materials after plasma treatment and the subsequent silylation repair.

Improvement of Gate Dielectric Integrity Using O2 Plasma Treatment Prior to Atomic Layer Deposition on Chemical Vapor Deposition Grown Graphene.

We report that oxygen plasma treatment of CVD-grown graphene can improve the integrity of an aluminum oxide layer deposited by atomic layer deposition. There is an optimum process window for treatment with O2 plasma which does not cause serious degradation in the quality of the graphene, but provides significant improvement in the gate dielectric integrity in relation to capacitance uniformity, leakage current, and dielectric breakdown voltage.

Growth, strain relaxation properties and high-κ dielectric integration of mixed-anion GaAs1-ySby metamorphic materials

Mixed-anion, GaAs1-ySby metamorphic materials with a wide range of antimony (Sb) compositions extending from 15% to 62%, were grown by solid source molecular beam epitaxy (MBE) on GaAs substrates. The impact of different growth parameters on the Sb composition in GaAs1-ySby materials was systemically investigated. The Sb composition was well-controlled by carefully optimizing the As/Ga ratio, the Sb/Ga ratio, and the substrate temperature during the MBE growth process. High-resolution x-ray diffraction demonstrated a quasi-complete strain relaxation within each composition of GaAs1-ySby. Atomic force microscopy exhibited smooth surface morphologies across the wide range of Sb compositions in the GaAs1-ySby structures. Selected high-κ dielectric materials, Al2O3, HfO2, and Ta2O5 were deposited using atomic layer deposition on the GaAs0.38Sb0.62 material, and their respective band alignment properties were investigated by x-ray photoelectron spectroscopy (XPS). Detailed XPS analysis revealed a valence band offset of &amp;gt;2 eV for all three dielectric materials on GaAs0.38Sb0.62, indicating the potential of utilizing these dielectrics on GaAs0.38Sb0.62 for p-type metal-oxide-semiconductor (MOS) applications. Moreover, both Al2O3 and HfO2 showed a conduction band offset of &amp;gt;2 eV on GaAs0.38Sb0.62, suggesting these two dielectrics can also be used for n-type MOS applications. The well-controlled Sb composition in several GaAs1-ySby material systems and the detailed band alignment analysis of multiple high-κ dielectric materials on a fixed Sb composition, GaAs0.38Sb0.62, provides a pathway to utilize GaAs1-ySby materials in future microelectronic and optoelectronic applications.

Diffusion coefficient in transformer pressboard insulation part 1: non impregnated pressboard

Water is harmful for transformers; the dynamic behavior of moisture influences the dielectric integrity and insulation aging in a transformer on operation. In this paper, the determination of the diffusion coefficient of moisture in transformer pressboard is tackled. This work has been focused in analyzing non oil-impregnated pressboard, so the obtained coefficient is useful for studying the processes of transformer drying in factory. Drying experiments were developed in a thermogravimetric analyzer on nonimpregnated samples of pressboard subjected to different drying temperatures. The experimental conditions were simulated by means of a diffusion model implemented by means of Finite Element Method. The comparison between estimated and measured values allows drawing conclusions about the accuracy of the proposed coefficient.

Diffusion coefficient in transformer pressboard insulation part 1: non impregnated pressboard

Water is harmful for transformers; the dynamic behavior of moisture influences the dielectric integrity and insulation aging in a transformer on operation. In this paper, the determination of the diffusion coefficient of moisture in transformer pressboard is tackled. This work has been focused in analyzing non oil-impregnated pressboard, so the obtained coefficient is useful for studying the processes of transformer drying in factory. Drying experiments were developed in a thermogravimetric analyzer on nonimpregnated samples of pressboard subjected to different drying temperatures. The experimental conditions were simulated by means of a diffusion model implemented by means of Finite Element Method. The comparison between estimated and measured values allows drawing conclusions about the accuracy of the proposed coefficient.

Interfacial band alignment and structural properties of nanoscale TiO2 thin films for integration with epitaxial crystallographic oriented germanium

We have investigated the structural and band alignment properties of nanoscale titanium dioxide (TiO2) thin films deposited on epitaxial crystallographic oriented Ge layers grown on (100), (110), and (111)A GaAs substrates by molecular beam epitaxy. The TiO2 thin films deposited at low temperature by physical vapor deposition were found to be amorphous in nature, and high-resolution transmission electron microscopy confirmed a sharp heterointerface between the TiO2 thin film and the epitaxially grown Ge with no traceable interfacial layer. A comprehensive assessment on the effect of substrate orientation on the band alignment at the TiO2/Ge heterointerface is presented by utilizing x-ray photoelectron spectroscopy and spectroscopic ellipsometry. A band-gap of 3.33 ± 0.02 eV was determined for the amorphous TiO2 thin film from the Tauc plot. Irrespective of the crystallographic orientation of the epitaxial Ge layer, a sufficient valence band-offset of greater than 2 eV was obtained at the TiO2/Ge heterointerface while the corresponding conduction band-offsets for the aforementioned TiO2/Ge system were found to be smaller than 1 eV. A comparative assessment on the effect of Ge substrate orientation revealed a valence band-offset relation of ΔEV(100) &amp;gt; ΔEV(111) &amp;gt; ΔEV(110) and a conduction band-offset relation of ΔEC(110) &amp;gt; ΔEC(111) &amp;gt; ΔEC(100). These band-offset parameters are of critical importance and will provide key insight for the design and performance analysis of TiO2 for potential high-κ dielectric integration and for future metal-insulator-semiconductor contact applications with next generation of Ge based metal-oxide field-effect transistors.

Packaging Materials for Flip Chip and WLP: Underfill Design Using FEM for FC-BGA, FC-CSP, and Moving Towards 2.5/3D.

As technology nodes progress to 16/14nm and beyond underfill materials are presented with the significantly challenging task of maintaining bump protection while ensuring low warpage for ultra low-K dielectric (ULK/ELK) integrity. This challenge is further complicated by the trend toward RoHS compliancy (lead-free) and an ever increasing die size (beyond 25x25mm). Through extensive research and testing, several specifically formulated underfill materials were determined acceptable solutions for these complex issues. As technology nodes progress to smaller processes high stress concentrations are seen at the dielectric layer during thermal cycling. This stress is a typical result of a high glass transition temperature (Tg) / high strength material that often leads delamination or a cracking failure mode of the thin dielectric layer. Too low of a Tg presents a high stress concentration on the bumps which once again constitutes failure, this time, however, the crack is typically seen at the bump location. This high stress concentration seen at the bumps is more significant when lead free bumps are considered due to their inherent fragile nature. Underfill materials must now be specifically optimized for variable package conditions to solve these failure modes for a large variation of package designs. Desired material properties must be quickly calculated using finite element methods. This paper will discuss solutions to typical failure modes currently seen in reliability testing of present and future technologies.

Impact of surface treatments on high-κ dielectric integration with Ga-polar and N-polar GaN

Gallium- and nitrogen-polar GaN surfaces are subjected to a variety of pretreatments, including oxidation, before the application of high-κ dielectrics by atomic layer deposition (ALD) in order to assess the “best” preparation of smooth, clean, and electrically high-performing dielectric semiconductor interfaces. In terms of topographical and chemical cleanliness, a pretreatment with a wet chemical piranha etch (H2SO4:H2O2) was found to be optimum for both surfaces, and additionally, (NH4)2S is effective for N-polar surfaces. Both thermal and plasma oxidations were employed for controlled growth of native oxides. For Ga-polar surfaces, all native oxides were as smooth as pretreated surfaces, while for N-polar surfaces, all native oxides are much rougher except for very short, high temperature oxidations. ALD Al2O3 films on Ga-polar surfaces are smoother for pretreated surfaces than for as-received surfaces, whereas for N-polar surfaces the opposite is true. In general, ALD HfO2 films on Ga-polar surfaces are rougher (0.8 nm rms) than Al2O3 films (0.1 nm rms), whereas for piranha treated N-polar surfaces, HfO2 films are smoother than Al2O3 films. For Ga-polar surfaces, capacitance–voltage measurements of simple Al2O3 (measured κ = 9) capacitors show the smallest hysteresis for unintentionally oxidized surfaces (0.37 V), whereas simple HfO2 (measured κ = 14) capacitors show the smallest hysteresis for a thermal GaOx at the interface (0.1 V). In both cases, the thicker the GaOx at the interface the larger the negative threshold voltage shift—suggesting an electron trap. Calculated total trapped charges associated with the dielectrics range from 3.2 × 1011 cm−2 (for HfO2 on thermally oxidized GaN) to 1 × 1012 cm−2 for Al2O3 on thermally oxidized GaN and HfO2 on plasma oxidized GaN. Finally, the leakage current density for nearly all capacitors is &amp;lt;10−5 A-cm−2 at +8 V bias.

One-Time Programmable Memory Based on ${\rm ZrTiO}_{x}$ Antifuse for Crossbar Memory Application Featuring High Speed Operation and Low Power Consumption

TaN/ZrTiOx/Pt metal-insulator-metal structure was employed as the platform to evaluate the eligibility for antifuse one-time programmable (OTP) memory applications, and the impact of O2 plasma on device performance was also discussed. Owing to the oxygen radicals that enhance the dielectric integrity, the voltage for state switching increases with O2 plasma treatment. Memory cells without plasma treatment demonstrate promising characteristics for OTP memory applications in terms of a low dc switching voltage of 2 V, high programming speed of 60 ns, high read endurance up to 106 reading cycles, and desirable retention time and low switching power density of 6.4 mW/cm2. The memory cell technology not only exhibits the prominent performance which is advantageous over other dielectrics reported in the literature, but it also possesses the capability to from stackable 3-D architecture.

Integration of High-k Dielectrics on Epitaxial (100), (110) and (111) Germanium for Multifunctional Devices

not Available.

(Invited) Fundamentals in MoS2 Transistors: Dielectric, Scaling and Metal Contacts

The rise of two-dimensional (2D) crystals has given new challenges and opportunities to the device research. The semiconducting MoS2 has been considered as a promising ultrathin body channel for future microelectronic and optoelectronic devices. In this paper, we focus on the fundamental device properties in MoS2 transistors. In the first part we introduce the dielectric integration on MoS2 and other 2D crystals by atomic layer deposition, revealing the similarities and differences of dielectric integration on bulk and 2D crystals. Then we discuss scaling of channel length and width of MoS2 transistors. We also present the different metal contacts on MoS2, showing Fermi level pinning at metal/2D interfaces. Finally we demonstrate a statistical study on CVD based single layer MoS2 transistors, therefore to show potentials and limitations on these 2D crystals in device applications.

(Invited) Integration of High-κ Dielectrics on Epitaxial (100), (110) and (111) Germanium for Multifunctional Devices

With continued scaling of Si CMOS technology, new channel materials and device architectures are needed to address power consumption and constrained high-speed operation. With the demonstration of n-channel III-V transistors, the development of equivalent p-channel transistor is mandatory to realize energyefficient CMOS logic. The bulk transport properties of Ge make it an ideal candidate for p-channel transistor. The ultra-high hole mobility Ge can be realized through a III-V/Ge/III-V transistor configuration with different surface orientations would enable much faster switching, thus addressing dynamic power consumption, while the superior high- κ gate dielectric and larger bandgap barrier would help minimize OFF-state leakage. This paper discusses the i) in-situ growth of III-V/Ge/III-V heterostructure, ii) tailor-made surface orientations of Ge enable to achieve both high-hole and high-electron mobilities, and iii) band offsets of high- κ dielectrics on crystallographic oriented epitaxial (100)Ge, (110)Ge, and (111)Ge layers using solid state molecular beam epitaxy.

Pre- and post-breakdown electrical studies in ultrathin Al2O3 films by conductive atomic force microscopy

The loss of local dielectric integrity in ultrathin Al2O3 films grown by atomic layer deposition is investigated using conducting atomic force microscopy. I–V spectra acquired at different regions of the samples by constant and ramping voltage stress are analyzed for their pre- and post-breakdown signatures. Based on these observations, the thickness dependent dielectric reliability and failure mechanism are discussed. Our results show that remarkable enhancement in breakdown electric field as high as 130 MV/cm is observed for ultrathin films of thickness less than 1 nm.

Subthreshold analysis of nanoscale FinFETs for ultra low power application using high-k materials

Fin Field Effect Transistors (FinFETs) are used for Complementary Metal Oxide Semiconductor applications beyond the 45 nm node of the Semiconductor Industry Association (SIA) roadmap because of their excellent scalability and better immunity to short channel effects. This article examines the impact of high-k dielectrics on FinFETs. The FinFET device performance is analysed for On Current, Off Current, I on/I off ratio, drain induced barrier lowering, electrostatic potential along the channel, electric field along the channel, transconductance, output resistance, intrinsic gain, gate capacitance and transconductance generation factor, by replacing the conventional silicon dioxide gate dielectric material, with various high dielectric constant materials. Nanosize ZrO2 (zirconium-di-oxide) is found out to be the best alternative for SiO2 (silicon-di-oxide). It is also observed that the integration of high-k dielectrics in the devices significantly reduces the short channel effects and leakage current. The suitability of nanoscale FinFETs is observed with the help of an inverter circuit and their gain values are calculated for circuit applications.