Die Thickness Research Articles

Evaluation of the impact of the physical dimensions and material of the semiconductor chip on the reliability of Sn3.5Ag solder interconnect in power electronic module: A finite element analysis perspective

This paper primarily focuses on an evaluation study for the temperature cycling capability of tin silver solder interconnect in power electronic applications by the impact of die dimensions and die material properties. The study was investigated on finite element analysis perspective on chip/solder/substrate structure. A commercially available chip was chosen in the finite element analysis (FEA) as the nominal base die. Two thermal cycle profiles were utilised. The effect of die area, die thickness and material properties (Si and SiC) on the thermal cycling capability of the solder layer was investigated from FEA perspective. From the FEA, it was concluded that decrease in die thickness resulting in increment of thermal cycling capability of solder layer for both material (Si and SiC). Increase in die area increases the thermal cycling capability of solder. For higher ΔT thermal cycle, solder under SiC die perform better than solder under Si die in terms of thermal cycling capability. When the die thickness become smaller than a threshold value of the thermal cycle regime, solder under Si die have better thermal cycling capability than solder under SiC die. Additionally a parametric study was undertaken for a SiC chip/substrate structure under high ∆T temperature cycling profile for solder layer geometric parameter (wetting angle, titling angle and thickness). From the parametric study which utilised design of experiments (DoE), a wavelet radial basis surrogate model was generated. A sensitivity analysis was performed on surrogate model in order to identify the most influencing parameter. From the sensitivity analysis, it was concluded that wetting angle and solder layer thickness of solder layer have significant impact on the thermal cycling capability of the solder layer.

Development and Challenges of Warpage for Fan-Out Wafer-Level Package Technology

Abstract Fan-out wafer-level-packaging (FO-WLP) technology has been widely investigated recently with its advantages of thin form factor structure, cost effectiveness and high performance for wide range applications. Reducing wafer warpage is one of the most challenging needs to be addressed for success on subsequent processes. Therefore, the majority of studies focus on the ratio of die and compound thickness, structure design. In order to optimize the warpage for success on subsequent processes, it is indispensable to consider whole wafer process including thermal loading and stress. In this study, reducdution of wafer warpage at each process was proposed in terms of material selection, and process optimization through finite element analysis (FEA) and experiment. Wafer process dependent modeling results were validated by experimental measurement data. The mutual relationship and effects of material property, compound thickness, and corresponding thermal influences were both investigated and addressed. Key parameters were identified based on FEA modeling results: thickness ratio of die/compound andmolding compound materials. Therefore, the geometry design with balanced die/compound ratio is optimal for warpage improvement. The effect of process will be discussed and should be considered for future package warpage characterization. Such findings have been successfully used in process optimization to reduce wafer warapge after grinding process.

Impact of die thinning on the thermal performance of a central TSV bus in a 3D stacked circuit

In three-dimensional integrated circuits (3DICs), aggressive wafer-thinning can lead to large thermal gradients. It is crucial to understand the interaction between process parameters, such as wafer thickness, and the temperature profile in order to design high-performance 3DICs. In this paper we examine how the temperature profile of through-silicon via (TSV) bus driver/receiver cells are impacted by die thinning. While die thinning limits the ability for heat to diffuse into the wafer, it can also decrease the capacitance of the TSV which in turn decreases the driver׳s power, leading to an overall lower working temperature in some circumstances. In this work we have investigated the thermal effects of stacking 2–8 thinned ICs with TSVs, over a range of die thicknesses from 100μm to 25μm. Decreasing the die thickness from 100μm to 50μm provided the best balance with a 20% reduction in bus power at a cost of less than a 2% increase in driver temperature for all cases between 2 and 8 tiers.

Investigation of factors affecting backside hotspot localization in infrared lock-in thermography

Infrared lock-in thermography (IR-LIT) is a fault localization technique that serves the purpose of detecting a local heat source or hotspot emitted by the faulty area. Performing backside hotspot localization overcomes the limitation during frontside hotspot localization, especially for shorted areas that emit a low heat source. In order to produce better hotspot localization from the package backside, it is important to study more of the factors affecting backside hotspot localization, including the power settings of the device, the lock-in frequency, and the die thickness of the packages. Power packages are inspected using a tool with varying power and frequency settings. The results are collected by observing the size of the hotspot and by recording the time taken for the hotspot to appear. To investigate the die thickness, the die surface is grinded from the backside of the die and the thickness of the die was measured using x-rays. The relationship between the power settings, the frequency settings, and the die thickness does show significant changes to the hotspot size and the time taken to generate a hotspot.

Evaluation of Die Strength by Using Finite Element Method With Experiment Validation

3-D chip stacking packaging is becoming increasingly popular in the electronics packaging industry because the demand of current market has focused on cheaper products with higher performance characteristics and smaller form factors. Silicon wafers must be ground using wafer-thinning processes to achieve smaller packaging sizes. However, cracks may form in the silicon chips during stacking or while the device is in use. In this paper, the ball-breaker test is used to determine the maximum allowable force on a (1 0 0) silicon die. Finite element (FE) analysis using the commercial software ANSYS/LS-DYNA3-D is introduced to calculate the strength of the silicon die and compared with the experimental findings shows that the results are consistent with Hertzian contact theory. The effects of silicon die thickness and foundation material on the silicon die strength are also discussed in this paper. As the applied force increases, a crack appears on the edge of the contact area and propagates within the die. A decrease in die thickness results in the formation of radial cracks on the bottom surface as well as significant bending effects on the test die. The initial failure may originate from the radial crack and propagate toward the top surface of the die leading to die breakage. The strengths determined in this experiment decrease as the test die becomes thinner. Furthermore, if the insignificant bending behavior is observed, simulation results show that the maximum allowable force on a silicon die increases when a softer foundation material is used. However, a thin test die placed on a soft material is considerably easy to break because the tensile stress on the bottom surface of the die caused by the rapid increase in bending behavior significantly affects die breakage.

금형두께에 대한 1차 구조해석 결과를 기반으로 한 2차 최적화 해석에 관한 연구

기존의 구조해석은 탄성해석을 일반적으로 실무에서 주축으로 해왔다. 때문에 보다 정밀한 해석을 위하여 재료와 기하학적인 비선형을 고려한 해석의 필요성이 끊임없이 대두되어 왔다. 따라서 본 연구에서는 간단한 모델을 제작하여 비선 형 원리를 적용한 최적화를 수행하여 기존의 구조해석의 경험자들은 누구나 용이하게 해석을 수행할 수 있는 이론과 방법을 제시하는데 있다. 본 연구에서 소개되는 모델은 금형 다이리브에 적용될 수 있도록 전단하중에 대하여 충분한 강도로 Strain, Stress가 적게 발생하게 하여, 초기에는 Strain, Stress가 크기에 맞게 형상을 재구성하고 Hyperstudy와 Abaqus 연동에 의한 비선형으로 해석하고 제품에서 허용되는 최대, 최소 Stress 범위와 최소 Strain을 갖는 조건하에서 일정한 증가치를 만들게 하였다. 실험 모델에서 Plate 두께가 40 Newton의 힘으로 주어질 때 Iteration 처리로 금형 두께에 따른 Stress와 Strain에 대한 금형두께에 적용하고자 했을 때 7∼8mm 두께가 최적화라는 결론을 얻을 수 있었다.

Thermal Modeling and Life Prediction of Water-Cooled Hybrid Concentrating Photovoltaic/Thermal Collectors

In this paper, a multiphysics, finite element computational model for a hybrid concentrating photovoltaic/thermal (CPV/T) water collector is developed. The collector consists of a solar concentrator, 18 single junction germanium cells connected in series, and a water channel cooling system with heat-recovery capability. The electrical characteristics of the entire module are obtained from an equivalent electrical model for a single solar cell. A detailed thermal and electrical model is developed to calculate the thermal and electrical characteristics of the collector at different water flow rates. These characteristics include the system temperature distribution, outlet water temperature and the thermal and electrical efficiencies. The model is used to study the effect of flow rate on the efficiencies. It is found that both efficiencies improve as the flow rate increases up to a point (0.03 m/s), and after that point remain at relatively constant levels. However, as the flow rate increases the outlet water temperature decreases, reducing the quality of the extracted thermal energy. In addition to the thermal and electrical modeling, finite element analysis is used to estimate the fatigue life of the module based on the different temperature profiles obtained from the thermal model at flow rates of 0.01 m/s and 0.03 m/s. Results show that for the higher flow rate, the outlet water temperature decreases, but the fatigue life improves. Based on the fatigue life model predictions, it is shown that the thickness of die attach layer must be increased for high outlet temperature applications of the hybrid CPV/T collector.

Two-Dimensional Flex Sensor Exploiting Stacked Ultrathin Chips

A new concept for mechanically flexible stress and flex sensors is presented. A stack of two ultrathin chips is exploited to compensate both thermal effects and the vertical piezoresistive effect. By tailoring the thickness of the top die, the active devices of the bottom chip become stress compensated, whereas the devices of the top chip receive maximum stress. The structural arrangement enforces that the apparent vertical stresses and the temperatures of both dies are basically identical. Thus, the differential signal of both dies provides a temperature-compensated information about the 2-D stress and flexure.

Effects of Material Properties and Thickness of Die Attach on Package Delamination of IC Packages

Finite element method is carried out to calculate the fracture mechanics parameter of interfacial cracking of TSOP (Thin Small Outline Package). Fracture mechanics approach together with finite element results are used to study the impacts of material properties and thickness of die attach on the energy release rate at crack tip of interfacial delamination between die pad and die attach. The results show that larger Young’s modulus, smaller CTE as well thinner thickness of die attach can reduce ERR at crack tip during reflow.

DEVELOPMENT OF A GRANULAR PROCESSING MACHINE

The aim of this study was to develop and testing of granular-processing machine for poultry fodder. The tested parameters were: (1) die speeds of 160, 180, 200, 220, 240 and 260 rpm, the die speeds were 80, 90, 100, 110, 120 and 130 rpm (2) hole diameters of 3, 4 and 5 mm (3) Die thickness of 8, 12, 15, 20 and 25 mm. and (4) Moisture content of fodder mixture 5 %, 10% and 15%. The optimum conditions of developed machine were: (1) Die-hole diameter of 3, 4 and 5 mm, (2) Die thickness of 8 mm, (3) Die speed of 220 rpm, (4) Fodder moisture-content of 10 % and (4) Granular dry-duration of 69 h. The obtained results in optimum conditions can be summarized as follows: Granular productivity ranged between 185 – 276 kg/h, Granular losses ranged between 3.03 – 3.78 %, real density ranged between 1.1469 – 1.1491 g / cm3, Granular durability ranged between 88.9 – 90.7 and Machine power ranged between 8.89 – 10.05 kW. The variables affecting the granular productivity, total losses, density were combined into dimensionless groups. The general equations were formulated inside the paper. The production costs at optimum conditions were 12 to 11.71 64.84, 54.17 and 43.84 L.E./ton for die-hole diameters 3 and 4 and 5 mm respectively.

Effects of the pelleting conditions on chemical composition and sugar yield of corn stover, big bluestem, wheat straw, and sorghum stalk pellets

Pelleting of biomass can increase their bulk density and thus improve storability and reduce transportation costs. The objective of this research was to determine the effects of the pelleting conditions on chemical composition and fermentable sugar yield of the biomass. Corn stover, wheat straw, big bluestem, and sorghum stalks were used for this study. Dilute sulfuric acid was used for biomass pretreatment. Accellerase 1500™ was used for cellulose hydrolysis. Effects of mill screen size, die thickness, and L/D ratio of die on chemical compositions and sugar yield were determined. Glucan content of the biomass was positively affected by die thickness and negatively affected by mill screen size. Opposite trend was observed for xylan content. Wheat straw pellets had the highest sugar yield (92.5-94.1%) and big bluestem pellets had the lowest sugar yield (83.6-91.1%). Optimum pelleting condition is 6.5 mm screen size and 44.5 mm die thickness.

Effects of Material Properties and Thickness of Die Attach on Warpage and Stresses of TSOP

The assembly of plastic electronic package requires a sequence of process steps. Every process step induces thermal residual deformation and stresses on the assembled components, which cause mechanical effects on the subsequent process step. Processing model with considering the effect of chemical shrinkage on molding compound is built to simulate the package warpage and stresses in assembly. The processing model, a nonlinear model with element birth and death used to activate and deactivate the processing materials, can more realistically simulate a series of assembly processes in a plastic package. The stresses in package components are primary factor for the damage of package. The induced package stresses can cause the delamination between die/die attach interface or die attach/die pad interface. In this study, effects of material properties as well thickness of die attach on warpage and stresses of TSOP (Thin Small Outline Package) during assembly are discussed.

Effects of Different Die and Epoxy Thickness to the QFN Package

Quad Flat No-Lead or QFN is able to provide lighter, thinner and higher performance packaging requirement with its exposed pad and leads at the package bottom for better heat dissipation. However, QFN packages possess certain weaknesses. QFN package failures are related to crack and delaminating, such as die cracking, moulding compound and solder mask interfacial delaminating. From previous projects, the epoxy thickness and die thickness plays an important role in reducing failures in QFN package. The objective of this project is to observe the effects of die and epoxy thickness. The effects on QFN are measured in the die and lead frame part. Stress towards the die is also measured: including thermal, first principle and Von Misses stress. The structural optimization is based on the Finite Element Analysis (FEA). By using ANSYS 10.0, six models were constructed, where three models were built to analyse in thickness of epoxy, and another three to study the effects on die thickness. The effect was measured by the value stress (first principle stress and Von Misses stress) and thermal strain effect, which will lead to a result of how the dimensions of the packaging will give a better tolerance towards stress.

Micro Structure Observation and Reliability Behavior of Peripheral Flip Chip Interconnections with Solder-Capped Cu Pillar Bumps

PoP (Package on Package) structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones. However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 μm or less, an ultra-fine-pitch flip chip interconnection technique is required. The C4 (Controlled Collapse Chip Connection) flip chip technology is widely used in area array flip chip packages. The C4 was named after the four initial characters which are C of Controlled Collapse Chip Connection. The collapse of the molten solder is controlled by the individual opening of solder resist on each pad on the substrate so that the chip can be connected onto the substrate. However, C4 is not suitable in the ultra-fine-pitch flip chips because the such a individual opening which is suitable for the ultra-fine-pitch cannot be made on the substraete. Instead of the C4 flip chip technology, the new interconnection technique was developed using the solder capped Cu pillar bumps. It is very easy to control the space between the die and the substrate by adjusting the Cu pillar height even when a large slit window opening exists on a group of pads on the substrate. Since the collapse control of the solder bumps is not necessary, we call the process C2 (Chip Connection). The C2 was named after the two initial characters which are C of Chip Connection. The solder capped Cu pillar bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preservative), by reflow with no-clean processes. This technology creates the SMT (Surface Mount Technology)/flip chip hybrid assembly for SoP (System on Package) use. We have produced 50 μm pitch interconnections and observed the micro structure and tested their reliability. Some voids in the solder joint were observed after the reflow process. The results of warpage measurements and FEM (Finite Element Method) analyses suggest that these voids are the shrinkage voids caused by the wide temperature range of the solder liquid phase and the substrate warpage. Since they are not the stress induced voids, they didn't affect the reliability test. The increase in interconnection resistance during the reliability test was compared between the C2 interconnection and Au stud-solder interconnection. Since the resistance increase of the C2 interconnection is much smaller than that for the Au stud-solder interconnection, it is clear that the C2 flip chip technology provides robust solder connections at low cost. Also the C2 structure with a low-k device was evaluated and no failures were observed at 1,500 cycles in the TC (Thermal Cycle) test. In addition to the fine-pitch interconnections, a die thickness of 70 μm is required to reduce the final stack height. The reliability performance of the C2 flip chip with the die thicknesses 20 μm, 70 μm and 150 μm was also discussed using a PEG (Post-Encapsulation Grinding) method in which the die is ground to less than 70 μm after joining and underfilling. Finally the electromigration tests were performed on the 80 μm pitch C2 interconnection. The tests showed that the solder capped Cu pillar structure has high endurance against electromigration and no failure data was recorded up to 1,000 hrs with several electromigration conditions regardless the direction of electron flow.

Design and Development of Multi-Die Laterally Placed and Vertically Stacked Embedded Micro-Wafer-Level Packages

Two embedded micro-wafer-level packages (EMWLP) with 1) laterally placed and 2) vertically stacked thin dies are designed and developed. Three-dimensional stacking of thin dies is demonstrated as progressive miniaturization driver for multi-chip EMWLP. Both the developed packages have dimensions of 10 mm × 10 mm × 0.4 mm and solder ball pitch of 0.4 mm. As part of the development several key processes like thin die stacking, 8-in wafer encapsulation using compression molding, low-temperature dielectric with processing temperature less than 200°C have been developed. The EMWLP components success fully pass 1000 air to air thermal cycling (-40°C to 125°C), unbiased highly accelerated stress testing (HAST) and moisture sensitivity level (MSL3) tests. Developed EMWLP also show good board level TC (>; 1000 cycles) and drop test reliability results. Integration of thin film passives like inductors and capacitors are also demonstrated on EMWLP platform. Developed thin film passives show a higher Q-factor when compared to passives on high resistivity silicon platform. Thermo-mechanical simulation studies on developed EMWLP demonstrate that systemic control over die, RDL, and package thicknesses can lead to designs with improved mechanical reliability.

Stress analysis of 3-dimensional IC package as function of structural design parameters

Solid Liquid Inter-Diffusion (SLID) is a technology that has recently been utilized to fabricate 3D ICs. Since application of this technology is in its infancy stages, manufacturability and reliability of these bonds are still under heavy investigations. This study presents an elastic–plastic finite element and analytical analyses that were implemented to evaluate effect of package design parameters on thermo-mechanical reliability of the SLID bonds and copper interconnects. A numerical experiment is designed in which several design parameters; die thickness, bond size, underfill stiffness and substrate thickness, are varied in 3 levels. Stress in SLID bonds and in copper interconnects were evaluated using the 3-dimensional finite element analysis as well as an analytical approach. The results show that die and substrate thicknesses are the most influential factors among the selected parameters on stress at the interface and on copper interconnects. Main effect results for stress analysis in SLID bonds using finite element shows that die thickness and underfill stiffness are the most influential factors in defining stress at SLID bonds. Results of the analytical approach confirm the finite element analysis. It is shown that effect of interconnect size and pitch is very small compared to die thickness. In average increasing die thickness increases both shear and peeling stresses at the interfaces and copper interconnects.

The Study of Flowing Balance with Multi-Cavity Die and Non-Uniform Thickness

This study aimed to create a multi-cavity and non-uniform thickness die casting for flowing balance. The die casting processes involved a hot-chamber die casting experiment and computer aided simulation to explore the flowing condition of the molten metal in the metal molding process. Computer-aided mould flow analysis software FLOW 3D V9.2 was applied to simulate the filling stage of zinc alloy in the mould cavities. The design parameters of the mould included four variables relating to the gate: width, position, shape, and thickness of cross-section. Analysis results shows that the primary goals of balance design include two things: (1) the flowing path of molten metal was shortest; (2) the mould cavity was easiest to fill with molten metal. The flowing balance design used analysis software to simulate the flowing condition of the air, which produced an air trap. The melting metal motive force pushed air into the slug well in order to reduce the production of pores. The experiment confirms the actual flowing situation of zinc alloy with a nearly 95% accuracy.

Structural design optimization for board-level drop reliability of wafer-level chip-scale packages

In this paper, the Taguchi optimization method is applied to obtain the optimal design in enhancing board-level drop reliability of a wafer-level chip-scale package (WLCSP) under JEDEC drop test condition B, which features a half-sine impact acceleration pulse with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. An L 9 (3 4) orthogonal array is arranged for the optimization of four control factors that involve compositions of solder alloys and thickness of die and polyimide passivation layers. The submodeling technique capable of dealing with path-dependent features, including elastoplastic responses of solder joints and structural nonlinearity under drop impacts, is applied so that delicate structures of passivation, under bump metallurgy (UBM), and redistribution line (RDL) in a WLCSP package can be taken into account. Effects of these control factors on the drop reliability of WLCSP are compared and ranked.

Investigations of Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages

We present in this paper parametric studies of board-level reliability of wafer-level chip-scale packages subjected to a specific pulse-controlled drop test condition. Eighteen experiment cells, constructed by varying joint pitch, die thickness, and die size, are proposed and examined numerically. The transient analysis follows the support excitation scheme and incorporates an implicit time integration solver. Numerical results indicate that the drop reliability of the package enhances as the die thickness as well as the die size decreases. Moreover, the package with smaller solder joints and a smaller joint pitch suffers a greater drop reliability concern.

Reliability Analysis in Flip Chip Package under Thermal Cycling

The material properties of underfill and substrate in flip chip package have temperature-dependent and moisture-sensitive characteristics. During the solder reflow process, the CTE mismatch in the package causes thermal stresses, which may reduce the reliability of the flip chip package. The package reliability can be improved by varying the die thickness, the fillet angle and the thickness of the underfill and by changing the underfill material. In this paper, the temperature- dependent properties of the underfill were established first. The flip chip reliability was then analyzed by finite element code ANSYS. Both underfill A and underfill B were used in the analysis. The results show that better reliability of the flip chip package was obtained for underfill A, for larger fillet angle of the underfill, for thinner die in the package, and for larger Young's modulus of underfill with linear elastic assumption. Also a hygrothermal preconditioning before thermal cycling reduces the reliability of the flip chip package.