Die Stacking Research Articles

Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs

Memory, especially DRAM, is one of the candidates to be considered in three-dimensional integrated circuit (3-D IC), and in particular, to be heterogeneously stacked with a system on chip (SOC) for mobile applications. Even though the memory is tested and repaired beforehand, the known good die (KGD) can become bad during the integration process. Traditional schemes may not be able to redo the repair and obtain a known good stack (KGS), let alone unused spares be reused. We propose an off-chip repair scheme to deal with the inaccessibility from outside of the memory die. Using a through silicon via (TSV) to access the redundancy control circuit (RCC), we reactivate the unused spares by overwriting their states as if the corresponding fuses are blown. Even when the row or column, which has already been repaired, is damaged again, we are able to replace it with a new spare. Our simulation using a 65 nm process technology shows that the maximum timing penalty of the off-chip repair is only 93ps, compared to the on-chip method. The area overhead is estimated to be 490 μm2 per fuse set by using a 5 μm diameter TSV process. Most importantly, the yield improvement of a two-die stacked memory can be over 50% with yield excursion reduced to 8%.

Determination of temperature distribution in three-dimensional integrated circuits (3D ICs) with unequally-sized die

There is much interest in 3D integrated circuits (3D IC) technology for vertical integration of multiple device planes in semiconductor devices. Stacking several device planes vertically offers significant electrical performance improvements. This can also lead to reduced design and manufacturing costs. Several 3D IC manufacturing and packaging approaches require adjacent die sizes to be different from one another since this facilitates differentiated manufacturing and design. However, it is expected that unequally-sized die may cause deteriorated thermal performance due to heat spreading and constriction. This manuscript presents a heat transfer model for predicting the three-dimensional temperature field in a multi-die 3D IC with unequally-sized die. This problem is solved iteratively using solutions of three simpler heat transfer problems outlined in the manuscript. Temperature fields predicted by the model are in close agreement with finite-element simulation results. The model is used to compare the thermal performance of unequally-sized die stacks with a uniformly-sized die stack. Results indicate that the greater the degree of non-uniformity in the die stack, the greater is the peak temperature rise. The model and results presented in this manuscript are expected to aid in the development of effective thermal design tools for 3D ICs.

Enabling Packaging Houses to Achieve 3D Integration without Interposers

The growth of small portable consumer electronics has increased the requirements of creating densely stacked packages with ever decreasing footprints while still increasing storage capacities as well as accessible memory. Traditional approaches to create these packages have included wire-bonding and Package on Package (PoP) as well as through Silicon Via (TSV). All of these methods present a solution to current system requirements, each with its own drawback. This paper will discuss a novel method in which a vertical 3D die stack can be created of similar an in some cases dissimilar die. The final 3D structure of stacked die will present no XY offset between any level of the die stack achieving the smallest possible form factor. This method also eliminates the requirements of creating an interposer for the electrical connection between layers. The final result is a completely vertical die stack with electrical connections drawn on the outside edges of the die stack which adds <400um total in either the X or Y axis of the package. We will discuss required equipment, the best known methods and the optimal materials required to achieve the final product as well as JEDEC reliability data proving package robustness, such as Temperature Cycle, biased-HAST and High Temperature Storage.

Quality and Reliability of 3D High-Performance Heterogeneous Integration through Die Stacking

This paper studies package reliability for the industry's first heterogeneous Stacked Silicon Interconnect (SSI) FPGA family (3D integration) delivering up to 2.78 Tb/s transceiver bandwidth. Each device is packaged on a low-temperature co-fired ceramic (LTCC) package for optimal signal integrity. 3D thermal-mechanical simulations are built to analyze package warpage, low-k stresses, microbumps and C4 bumps fatigue as well as BGA ball reliability. Different substrate sizes and designs, lid designs, lid materials and C4 bump underfill materials are investigated in order to optimize package reliability. LTCC ceramic package reduces fatigue in C4 bumps when increasing the risk for BGA balls to fail in thermal stressing. Hence, lid design and C4 bump underfill material are optimized to increase fatigue life for BGA balls. Simulation results indicate heterogeneous stacked-silicon (3D) integration is a reliable method to build very high-bandwidth multi-chip devices that exceed current monolithic capabilities.

Evaluating Thermal Cycling Fatigue Resistance for LED Chip-on-Board Applications

LED chip-on-board applications typically involve assembling an LED die stack directly on to a high thermal conductivity substrate such as a Metal Core PCB. If solder is used for die-substrate attach for such chip-on-board applications, one needs to consider the CTE mismatch between the die stack and the MCPCB and its impact on thermal cycle-induced creep fatigue of the solder material. This paper presents a methodology to compare relative performance of different solder materials with varying thermo-mechanical properties, and compare the impact of CTE mismatch and temperature swings on transient thermal properties and relative reliability of the solder attach materials. Implications for LED chip-on-board applications are discussed.

Multi-scale Simulation Methodology for Stress Assessment in 3D IC: Effect of Die Stacking on Device Performance

Potential challenges with managing mechanical stress distributions and the consequent effects on device performance for advanced 3D integrated circuit (IC) technologies are outlined. A set of physics-based compact models for a multi-scale simulation, to assess the mechanical stress across the device layers in silicon chips stacked and packaged with the 3D through-silicon-via (TSV) technology, is proposed. A calibration technique based on fitting to measured stress components and electrical characteristics of the test-chip devices is presented. For model validation, high-resolution strain measurements in Si channels of the test-chip devices are needed. At the nanoscale, the transmission electron microscopy (TEM) is the only technique available for sub-10 nm strain measurements so far.

Electrical and Mechanical Properties of Through-Silicon Vias and Bonding Layers in Stacked Wafers for 3D Integrated Circuits

Thermal stress issues in a three-dimensional (3D) stacked wafer system were examined using finite-element analysis of the stacked wafers. This paper elucidates the effects of the bonding dimensions on mechanical failure and the keep-away zone, where devices cannot be located because of the stress in the Si. The key factors in decreasing the thermal strain were the bonding diameter and thickness. When the bonding diameter decreased from 40 μm to 12 μm, the equivalent strain decreased by 83%. It is noteworthy that the keep-away zone also decreased from 17 μm to zero when the bonding diameter decreased from 40 μm to 12 μm. When the bonding thickness doubled, the equivalent strain decreased by 44%. The effects of the dimensions and arrangement of through-silicon vias (TSV) were also analyzed. Small TSV diameter and pitch are important to decrease the equivalent strain, especially when the amount of Cu per unit volume is fixed. When the TSV diameter and pitch decreased fourfold, the equivalent strain decreased by 70%. The effects of TSV height and the number of die stacks were not significant, because the underfill acted as a buffer against thermal strain.

Yield Enhancement by Bad-Die Recycling and Stacking With Though-Silicon Vias

3-D integration provides a means to overcome the difficulties in design and manufacturing of system-on-chip (SOC) and memory products. Introducing a short vertical interconnect, called through-silicon via (TSV), makes it feasible to repair and recycle bad dies by stacking. We propose a method to accomplish this using a dual-TSV hardwired switch (DTHS) in which the via-hole location is programmable. With the DTHS, we activate a spare and establish inter-die routing. The spare is nothing but a good part in another bad die. To be 3-D reparable, the design is partitioned into disjoint parts. The effort for the modification is minor in view of that a typical SOC is readily composed of modules with predefined functions and supply voltages. The DTHS is used: 1) to shut off power connections of both failed and unused parts; 2) to disconnect their signal paths; and 3) to redirect them to the selected good parts in the stacked dies. Despite the speed is degraded due to the extra load incurred by the DTHS, our simulation shows that the increase in delay time can be limited below 100 ps with an over-designed buffer which occupies 0.8% of the area of a 30 μm TSV, using a 65-nm CMOS process. The performance degradation turns out to be a necessary evil, since the increased height of the die stack leads to a thermal conductivity poorer than its 2-D counterpart. The 3-D patch die helps to shorten time-to-market and turn the irreparable dies profitable.

A liquid cooling solution for temperature redistribution in 3D IC architectures

The advancement of contemporary three-dimensional integrated circuit (3D IC) technologies offers a promising solution for the insatiable demand of the consumer electronics market. The increased complexity of 3D IC design permits the execution of multiple applications at greater speeds whilst remaining within the design constraints of energy consumption, yield and time-to-market. However, the increased computing performance and compact size may introduce a thermal barrier inhibiting performance, particularly in the case where multiple logic die are stacked and co-aligned hotspots are induced. To mitigate this thermal barrier a novel integrated active thermal solution is investigated in this paper whose purpose is to alleviate hotspots in a contemporary two-die 3D IC architecture. The solution employs a series of integrated microchannels, which permits the transfer of heat, via a coolant, from lower to upper strata. This microfluidic system is driven by a series of integrated AC electrokinetic pumps embedded in the channel walls. Recent advancements in electrokinetic micropump technology have allowed greater increases in fluid velocity – to an order of mm/s – while operating within the voltage constraints of a 3D IC. Numerically qualitative and quantitative temperature distributions are presented for a 3D IC chip design both with and without microchannels for a constant heat flux on the active layer of each silicon chip. The implementation of a microchannel network is shown to alter the thermal distribution map within a 3D IC package creating hot and cold zones with variations on temperature of −14.6°C≤ΔT≤9.8°C with a ΔTmax of −6.5°C in the silicon die stack (equivalent to a total maximum heat flux, qmax″, of approximately 112.5W/cm2). Increasing bulk fluid velocity, within the range 1.3mm/s≤uavg≤13mm/s, can vary the area of the cold zone enhancing heat transfer and reducing the temperature of the die stack without an overall temperature change in the package.

Fine grain thermal modeling and experimental validation of 3D-ICs

3D die stacking is a promising technique to allow miniaturization and performance enhancement of electronic systems. Key technologies for realizing 3D interconnect schemes are the realization of vertical connections, either through the Si die or through the multilayer interconnections. The complexity of these structures combined with reduced thermal spreading in the thinned dies complicate the thermal analysis of a stacked die structure. In this paper a methodology is presented to perform a detailed thermal analysis of stacked die packages including the complete back end of line structure (BEOL), interconnection between the dies and the complete electrical design layout of all the stacked dies. The calculations are performed by 3D numerical techniques and the approach allows importing the full electrical design of all the dies in the stack. The methodology is demonstrated on a 2 stacked die structure in a BGA package. For this case the influence of through-Si vias (TSVs) on the temperature distribution is studied. The modeling results are experimentally validated with a dedicated test vehicle. A thermal test chip with integrated heaters and diodes as thermals sensors is used to successfully validate the detailed temperature profile of the hot spots in the top die of the die stack.

Effect of Manufacturing Stresses to Die Attach Film Performance In Quad Flatpack No-Lead Stacked Die Packages

Effect of Manufacturing Stresses to Die Attach Film Performance In Quad Flatpack No-Lead Stacked Die Packages

A Neural Network-Based Prediction Model in Embedded Processes of Gold Wire Bonding Structure for Stacked Die Package

The trend in the consumer electronics market is to offer lighter, smaller outline, and more functional products, especially for portable products. This trend has pushed electronic packages to be thinner, with a lower profile and with multiple chips in one package. When the package becomes thinner, the space of the package correspondingly becomes an important issue. In order to obtain higher density and thinner package, we have to develop an embedded gold wire bonding assembly technology. It provides a simple structure with a thick adhesive layer to fix the upper layer die and bottom layer die gold wire. The developed technology can use exactly the same die size as for wire bonding interconnections without any additional processing. All electrical connections of the upper and the lower die are achieved by wire bonding to the substrate, independently. We have performed this stacking assembly by precise control of the die attach film layer thickness and low wire loop shape.

Effect of Manufacturing Stresses to Die Attach Film Performance In Quad Flatpack No-Lead Stacked Die Packages

Problem statement: Repeated heat cure during assembly processes affected the Die Attach Film (DAF) material properties and the effectiveness touched area that leads to weak die bonding and delamination. Suitable die attached condition and DAF material selection had been evaluated to achieve required reliability performance in the manufacturing of the 3D Quad Flat No-Lead (QFN) stacked die package. Approach: During this study, special attention was given to the development of the residual stresses due to mismatch in the coefficients of thermal expansion of different DAF materials. Both experimental and finite element method were employed to gain a better understanding in a stress development induced between two different type of DAF, different die attach temperature and during the manufacturing process. Differential scanning calorimetry (DSC) was used to measure the changes of heat flow characteristics for both types of DAF. The die bond strength results measured using shear testing machine were compared with the finite element method prediction. Results: Although both DAF samples achieved good reliability performance and passed the Moisture Sensitivity Level 3 test (MSL3) at reflow 260°C without any sign of delamination, numerical simulation had demonstrated that the stress development were increased exponentially as the die attach temperature increased. It showed that different DAF gave different values of stresses but presented the same trend which the lowest die attached temperature (100°C in comparison with 125°C and 150°C) gave more stress to the die and possibility that the die will have weak adhesion to the substrate was high. Conclusions/Recommendations: Therefore for this case, stress can be relieved by having higher die attached temperature with an adequate bonding force and time, however die attached temperature for both DAF must be used above the glass transition temperature (128°C for DAF A and 165°C for DAF B) and being controlled not to exceed the crystallization temperature (203°C for DAF A and 204°C for DAF B) of both DAF.

A Model of BGA Thermal Vias as an Example of Lumped Parameter Analysis in Thermal Modeling of SiPs and Stacked Die Packages

In this paper, a review of the different approaches to stationary thermal analysis of stacked die packages is presented, focusing on the opportunity to develop compact models suitable to be included in the design flow. Actually, although three-dimensional integration of the heat equation by numerical methods may provide an accurate estimate of the temperature distribution in the package, its main drawbacks lie in the relatively high computational cost and time consumption, together with the need of very experienced users. Simplified models are thus developed by gradually lumping thermal parameters of the various layers in order to attain a description of the device as a network of thermal resistances.

Wiresweep Reduction via Direct Cavity Injection During Encapsulation of Stacked Chip-Scale Packages

Abstract As packaging continues to offer challenges with variable stacked die configurations of increasing complexity, traditional transfer mold encapsulation faces challenges in defining a robust process window. A major concern is the problem of “wiresweep,” wherein deformation of the wirebond during the mold process can potentially cause shortcircuiting. Several prior studies have focused on qualifying the effects of various wirebond and mold process parameters on package wiresweep, but most of these studies are restricted to single (discrete) die packages. This paper attempts to fill this gap of knowledge by experimenting with a variety of test vehicles with different stacking configurations. Specifically, the effects of varying loop height, stack height, and mold compound type are quantified in terms of maximum wiresweep. We find that loop height can have a considerable effect on wiresweep, with the maximum wiresweep being reduced by half (from around 6% to less than 3%) simply by reducing the loop height. Additionally, the study finds that for a given mold process, higher die stacks tend to increase wiresweep, although a threshold stack height exists beyond which further stacking can reduce wiresweep. Lastly, the data suggest that the choice of mold compound can adversely impact wiresweep, especially for test vehicles with traditionally high wiresweep. Having identified these trends, semianalytical models from the literature are used to investigate the cause behind these observations. The analysis suggests that the mold front velocity has the major root impact on package wiresweep. To validate this hypothesis, the series of tests conducted earlier is repeated for a compression mold process, which provides greater control over the mold front velocity. As predicted by the model, significant reduction in wiresweep is achieved. Thus, the compression mold process seems to offer the opportunity for reducing wiresweep without any compromise in the complexity of the die stack.

Failure Analysis of Full Delamination on the Stacked Die Leaded Packages

There has been significant demand for stacked die technology during the past few years. The stacked die devices are mainly used in portable consumer products. This kind of silicon integration technology provides flexibility in space reduction, weight savings, and excellent electrical functionality. In this article, the stacked die construction was built into the leaded package. It was found that the test vehicles had full delamination at the lead-frame paddle/mold compound interface after 100 temperature cycles (−65°C to 150°C) with moisture preconditioning at level 3 (60°C at 60% relative humidity for 40 h) although the electrical test passed 1000 temperature cycles. The fishbone diagram was used to identify the possible failure root causes. The material, process, and design factors were extensively evaluated by the experiments and finite element analysis. The evaluation results showed that die attach paste voids were major factors affecting the package integrity and could produce the delamination initiation at the edge of the die attach paste and propagate down to the lead-frame paddle/mold compound interface due to high stress concentration and weak adhesion strength. The finite element analyses were implemented to address the stress distribution in the stacked die package and verified by the scanning acoustic microscope. It demonstrated that excellent package integrity could be obtained by applying the void-free die attach paste and improving the adhesion strength at the lead-frame paddle level.

DESIGN FOR BOARD LEVEL RELIABILITY OF A MINIATURIZED MEMS PACKAGE: STACKED DIE TQFN

International Journal of Computational Engineering ScienceVol. 04, No. 02, pp. 347-350 (2003) PackagingNo AccessDESIGN FOR BOARD LEVEL RELIABILITY OF A MINIATURIZED MEMS PACKAGE: STACKED DIE TQFNTONG Y. TEE, GIOVANNI FREZZA, MAYHUAN LIM, HUN S. NG, FEDERICO ZIGLIOLI, and ZHAOWEI ZHONGTONG Y. TEESTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , GIOVANNI FREZZASTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , MAYHUAN LIMSTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , HUN S. NGSTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , FEDERICO ZIGLIOLISTMicroelectronics, 629 Lorong 4/6 Toa Payoh, Singapore 319521, Singapore Search for more papers by this author , and ZHAOWEI ZHONGNanyang Technological University, School of MPE, 50 Nanyang Ave, Singapore 639798, Singapore Search for more papers by this author https://doi.org/10.1142/S1465876303001241Cited by:4 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractA new type of MEMS 3D package is introduced: stacked die Thick Quad Flat Non-lead (TQFN), for application as a multiple axis linear accelerometer. Both solder joint and die reliability during board level thermal cycling test are important concerns, as they affect the functionality and quality of the product. Design analyses are performed to study the effects of 12 key design variations in package dimensions and material properties, on solder joint reliability.Keywords:QFNStacked DieAccelerometerSolder Joint Reliability References R. Darveaux, Effect of Simulation Methodology on Solder Joint Crack Growth Correlation, Proc. 50th ECTC Conference, Las Vegas, NE (2000) 1048-1058 . Google Scholar T. Y. Tee, H. S. Ng, J. Diot, G. Frezza, R. Tiziani and G. Santospirito, Comprehensive Design Analysis of QFN and PowerQFN Packages for Enhanced Board Level Solder Joint Reliability, Proc. 52nd ECTC Conference, San Diego, CA (2002) 985-991 . Google Scholar T. Y. Tee, M. Lim, H. S. Ng, X. Baraton, D. Kaire and Z. W. Zhong, Design Analysis of Solder Joint Reliability for Stacked Die Mixed Flip-Chip and Wirebond BGA, Proc. 4th EPTC Conference, Singapore (2002) 391-397 . Google ScholarW. W. Lee, L. T. Nguyen and G. S. Selvaduray, Microelectronics Reliability 40, 231 (2000). Crossref, Google Scholar FiguresReferencesRelatedDetailsCited By 4Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packagesTong Yan Tee and Zhaowei Zhong1 Dec 2004 | Microelectronics Reliability, Vol. 44, No. 12Absolute and relative fatigue life prediction methodology for virtual qualification and design enhancement of lead-free BGA Hun Shen Ng, Tong Yan Tee, Kim Yong Goh, Jing-en Luan and T. Reinikainen et al.Design analysis of touch chip for enhanced package and board level reliability Tong Yan Tee, Hun Shen Ng, H. Siegel, R. Bond and Zhaowei Zhong4-Dimensional Design Analysis and Optimization of System-in-Package Tong Yan Tee, Hun Shen Ng, Jing-en Luan, Xueren Zhang and Kim Yong Goh et al. Recommended Vol. 04, No. 02 Metrics History KeywordsQFNStacked DieAccelerometerSolder Joint ReliabilityPDF download