Abstract

The advancement of contemporary three-dimensional integrated circuit (3D IC) technologies offers a promising solution for the insatiable demand of the consumer electronics market. The increased complexity of 3D IC design permits the execution of multiple applications at greater speeds whilst remaining within the design constraints of energy consumption, yield and time-to-market. However, the increased computing performance and compact size may introduce a thermal barrier inhibiting performance, particularly in the case where multiple logic die are stacked and co-aligned hotspots are induced. To mitigate this thermal barrier a novel integrated active thermal solution is investigated in this paper whose purpose is to alleviate hotspots in a contemporary two-die 3D IC architecture. The solution employs a series of integrated microchannels, which permits the transfer of heat, via a coolant, from lower to upper strata. This microfluidic system is driven by a series of integrated AC electrokinetic pumps embedded in the channel walls. Recent advancements in electrokinetic micropump technology have allowed greater increases in fluid velocity – to an order of mm/s – while operating within the voltage constraints of a 3D IC. Numerically qualitative and quantitative temperature distributions are presented for a 3D IC chip design both with and without microchannels for a constant heat flux on the active layer of each silicon chip. The implementation of a microchannel network is shown to alter the thermal distribution map within a 3D IC package creating hot and cold zones with variations on temperature of −14.6°C≤ΔT≤9.8°C with a ΔTmax of −6.5°C in the silicon die stack (equivalent to a total maximum heat flux, qmax″, of approximately 112.5W/cm2). Increasing bulk fluid velocity, within the range 1.3mm/s≤uavg≤13mm/s, can vary the area of the cold zone enhancing heat transfer and reducing the temperature of the die stack without an overall temperature change in the package.

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