Determination of temperature distribution in three-dimensional integrated circuits (3D ICs) with unequally-sized die

Abstract

There is much interest in 3D integrated circuits (3D IC) technology for vertical integration of multiple device planes in semiconductor devices. Stacking several device planes vertically offers significant electrical performance improvements. This can also lead to reduced design and manufacturing costs. Several 3D IC manufacturing and packaging approaches require adjacent die sizes to be different from one another since this facilitates differentiated manufacturing and design. However, it is expected that unequally-sized die may cause deteriorated thermal performance due to heat spreading and constriction. This manuscript presents a heat transfer model for predicting the three-dimensional temperature field in a multi-die 3D IC with unequally-sized die. This problem is solved iteratively using solutions of three simpler heat transfer problems outlined in the manuscript. Temperature fields predicted by the model are in close agreement with finite-element simulation results. The model is used to compare the thermal performance of unequally-sized die stacks with a uniformly-sized die stack. Results indicate that the greater the degree of non-uniformity in the die stack, the greater is the peak temperature rise. The model and results presented in this manuscript are expected to aid in the development of effective thermal design tools for 3D ICs.