Die Shear Force Research Articles

Robustness Improvement of Thermosonic Flip Chip Bonding to Device Chip Tilt

In this paper, we describe the robustness of thermosonic flip chip bonding when the bottom chip is tilted in the chip-on-chip assembly. Experiments were carried out using a bottom chip with 12 Au ball bumps and a top chip with Al pads. A bonding condition that causes gross sliding at the bonding interface was chosen to improve the robustness to chip tilt. The bottom chip was tilted around the axis perpendicular to the direction of the ultrasonic vibration. We found that die-shear force and the sum of the contact area between bumps and the top chip electrodes were constant in spite of tilting of the bottom chip. Although the contact area between each bump and top chip electrode depended on different bonding forces generated by bottom chip tilting, the fractional area of Au-Al alloy of each bonding area became nearly equal. These were caused by the deformation stress of the gold ball bump under the application ofultrasonic vibration being constant in the deformation range in this study.

Effect of Cooling Rate on Intermetallic Compounds Formation in Sn-Ag-Cu-In Solder

The effect of the cooling rate in bonding on IMCs formation and their morphology in the solder joint with Sn-3.0Ag-0.7Cu-5.0In (mass%) lead-free solder was investigated. As the substrate, the Cu plate and the Cu plate with electroplated Ni were prepared. Bonding was conducted in the vacuum atmosphere, and bonding temperature and time were 300°C and 10 minutes, respectively. The cooling rates in the bonding were changed from 0.02°C/s to 0.2°C/s. In both Cu/Cu and Cu/Ni joints, scallop-shaped IMCs form at the joint interfaces regardless of the cooling rate. In the Cu/Cu joint, Cu6(Sn,In)5 and Cu3(Sn,In) layers form at the joint interface. In the Cu/Ni joint, (Cu,Ni)6(Sn,In)5 and (Cu,Ni)3(Sn,In) layers form at the joint interface with Cu and the (Cu,Ni)6(Sn,In)5 layer forms at the joint interface with Ni. Die shear force of the Cu/Ni joints are a little larger than those of the Cu/Cu joints. Fracture occurs in the boundary between the scallop-shaped layer or the granular IMC layer and the layered IMC in both joints. The cooling rate from the peak temperature to solidification is an important factor to decide the shape of formed IMC. When the cooling rate is high and supercooling becomes large, formation of pillar-shaped IMCs occurs easily.

Influences of argon plasma cleaning on the die-shear force of chip and copper/polyimide flexible substrate assembly using a non-conductive film

A non-conductive film (NCF) and a thermal compression process were combined to assemble a chip onto a flexible substrate. To achieve direct bonding and to enhance the adhesion of a chip on the flexible substrate with NCF, argon plasma was used to clean copper electrodes over a flexible substrate. For flexible substrates which received argon plasma cleaning, low contact angles were obtained, and gold bumps directly contacted copper electrodes to form active input/output (I/O) paths, indicating the contaminants on the flexible substrate were removed and a clean bonding surface could be achieved. Neither delamination nor porosity was observed at the bonding interface between the NCF and copper electrodes. A sound bonding interface with satisfactory die-shear force was achieved. The argon plasma cleaning led to a significant improvement of the die-shear force of a chip bonded onto the flexible substrate using NCF.

Effect of Bonding Time and Bonding Temperature on Lead-Free Solder Joints Dispersed Pillar Shaped IMCs

The effects of the bonding time and temperature on microstructures and the joint strength of solder joints dispersed pillar shaped intermetallic compounds (IMCs) with Sn-3.0Ag-0.5Cu (mass%, SAC) and Sn-3.0Ag-0.7Cu-5.0In (mass%, SACI) alloys were investigated. The effects of the electrode type and the joint height on them were also investigated. In the Cu/Cu joint with SAC, the length of the pillar shaped IMC increased with increasing the bonding time although the effect of the bonding temperature on it was negligible. The thick joint height was effective to form pillar shaped IMCs in the joint. In the Cu/Ni joint with SAC, thin pillar shaped IMCs formed in the joint. In the joints with SACI, the high bonding temperature was effective to generate a large quantity of pillar shaped IMCs regardless of the electrode type. The small amount of In addition is effective to increase the nucleation site of the primary IMC and the thick joint height is effective to form finer pillar shaped IMCs in the joint. The die shear force measurement revealed that the pillar shape IMC such as to connect both sides is effective to improve the joint strength.

Effect of Added Elements on Microstructures and Joint Strength of Lead-Free Sn-Based Solder Joint Dispersed IMC Pillar

To create a high reliability solder joint using IMCs dispersed in the joint, the joints with four types of lead-free solder were investigated. The joint with Sn-3.0Ag-0.7Cu-5.0In (mass%) has high die shear force compared to other joints investigated, and the joint with the Ni-electroplated Cu bonded at 300 oC for 30 min showed the maximum die shear force due to formation of a large number of fine IMCs. In the joint with Sn-0.7Cu-0.05Ni (mass%), uniform dispersion of a large number of IMCs was achieved, although the die shear force of the joint is lower than that of the joint with Sn-3.0Ag-0.7Cu-5.0In. In the joint with Sn-5.0Sb (mass%), a solder area was remained in the center of the joint although a large number of columnar IMCs form at the joint interface. The die shear force of the joint with Sn-5.0Sb increased with increasing the bonding time due to formation and growth of IMCs. In the joint with Sn-3.0Ag-0.5Cu (mass%), IMCs formed at the joint interface and did not disperse in the entire joint.

Thermomechanical Assessment of Die-Attach Materials for Wide Bandgap Semiconductor Devices and Harsh Environment Applications

Currently, the demand by new application scenarios of increasing operating device temperatures in power systems is requiring new die-attach materials with higher melting points and suitable thermomechanical properties. This makes the die-attach material selection, die-attaching process, and thermomechanical evaluation a real challenge in nowadays power packaging technology. This paper presents a comparative analysis of the thermomechanical performance of high-temperature die-attach materials (sintered nano-Ag, AuGe, and PbSnAg) under harsh thermal cycling tests. This study is carried out using a test vehicle formed by four dice (considering Si and SiC semiconductors) and Cu substrates. Thermally cycled test vehicles have been thermomechanically evaluated using die-shear tests and acoustic microscopy inspections. Besides, special attention is paid to set up a nano-Ag sintering process, in which the effects of sintering pressure or substrate surface state (roughness and surface activation) on the die-attach layer are analyzed. As a main result, this study shows that the best die-attach adherence is obtained for nano-Ag when pressure is applied on the dice (using a specifically designed press) during the sintering process (11 MPa provided die-shear forces of 53 kgf). However, this die-attach presents a faster thermomechanical degradation under harsh thermal cycling tests than other considered high-temperature die-attach materials (AuGe and PbSnAg) and PbSnAg shows the best thermomechanical performances.

Transient Liquid Phase Sintering (TLPS) Conductive Adhesives for High Temperature Automotive Applications

Power electronics products such as inverters and converters involve the use of Thermal Interface Materials (TIMs) between high power packages and a heat exchanger for thermal management. Conventional TIMs such as thermal greases, gels, solders and phase change materials (PCMs) face challenges to meet the need of these products to operate reliably at much higher temperatures. This has driven the development of new TIMs such as Transient Liquid Phase Sintering (TLPS) Conductive Adhesives. TLPS adhesives have been developed for many potential applications due to various advantages like lead free, flux-less and particularly their low temperature processability , which enables the use of heat sensitive components in the design. With all these motivations, a project was launched and completed to assess TLPS adhesives as a unique TIM for high temperature automotive applications due to its high bulk thermal conductivity and metallic joint formation at interfaces. This paper reports the evaluation of three different TLPS conductive adhesives with different formulations. All the TLPS adhesives contain lead-free eutectic SnBi fillers, together with other fillers with much higher melting point (Tm) so as to process them using low temperature profiles. Different processing profiles were applied to process different TLPS adhesives. After processing, the assemblies could meet high temperature application requirements due to the shift of Tm of SnBi alloy from 139°C to a much higher value >200°C. Three different heat exchanger materials including bare Cu, Al and AlSiC with solder wettable surface finishes were assessed. X-ray was used to check void formation and Scanning Electron Microscopy (SEM) was conducted on the cross sections to study the quality of the whole metallurgical network. Die shear force was used to verify the joint strength. Thermal resistance measurement was carried out to verify thermal performance of TLPS assemblies. Thermal cycling test (−40 °C to +135 °C) had been performed to assess the reliability performance of the assemblies. TLPS samples built on Al and Cu substrates exhibited higher thermal resistance due to higher mis-match of coefficient of thermal expansion (CTE) with that of AlN, while TLPS samples assembled on AlSiC substrates were much more reliable and showed low thermal resistance throughout the thermal cycling test.

Reliability of TCT and HH/HT test performed in chips and flex substrates assembled by thermosonic flip-chip bonding process

With the adequate bonding parameters, a bonding load of 930gf, an ultrasonic power of 20.66W, a bonding temperature of 200°C and a bonding time of 0.3s, a sound bond with sufficient die–shear force was achieved in chips thermosonically bonded directly onto copper electrodes with a 0.5μm-thick nickel layer. After chips thermosonically bonded onto copper electrodes, the reliability of temperature cycling test (TCT) and high humidity/high temperature (HH/HT) test was evaluated. The reliability of TCT and HH/HT test demonstrates that gold bumps were firmly bonded onto copper electrodes over the flex substrates for subjected various test durations. Therefore, the reliability of TCT and HH/HT test for gold bumps thermosonically bonded directly onto copper electrodes should not be an important issue. During TCT, thermal stress at the interface between the gold bumps and bond pads of silicon chips caused crack at the interface. That is, the TCT degraded the die–shear forces of chips and flex substrate assemblies. The reliability of the TCT in chips thermosonically bonded onto flex substrates was dependent on the severity of crack. Similarly, crack and blisters that occurred at the bonding interface between gold bumps and bond pads of silicon chips after HH/HT tests of varying durations deteriorated the die–shear forces. Moistures penetrated into deposited layers of bond pads, deposited layers lost their adhesion, and cracks and blisters were formed as increasing the test durations. The reliability of TCT and HH/HT test must be improved to prevent crack at the bonding interface between the gold bumps and bond pads and to prevent moisture from penetrating into the deposited layers of bond pads, respectively.

Enhancement of the Bondability and Die-Shear Force of Chip–Flex Substrate Assemblies by Depositing a Nickel Layer on the Flex Substrate

A nickel layer and a silver bonding layer have been deposited on copper electrodes over flex substrates to improve the bondability and die-shear force performance of chip–flex substrate assemblies when using the thermosonic flip-chip bonding process. For bonding temperature of 200°C, the maximum die-shear force was achieved by combining parameter values of 20.66 W ultrasonic power, 625 gf bonding force, and 0.5 s bonding time. The improved bondability and die-shear force could be attributed to better transfer of ultrasonic power across the bonding interface during thermosonic flip-chip bonding, owing to the high rigidity of the copper electrodes provided by the nickel layer. Experimental results also indicated that high bonding load is necessary at elevated ultrasonic power range to provide firm contact between the bumps and electrodes to enable smooth ultrasonic power transfer across the bonding interface. Moreover, prolonged bonding time caused cracks between the bumps and flex substrate. Close examination of the fracture morphologies after die-shear testing and after ultrasonic separation provided insight into the die-shear force performance as influenced by the process parameters and by the deposition of the nickel layer on the copper electrodes over the flex substrate.

HTS and PCT Reliability of Chips and Flex Substrates Assembled Using a Thermosonic Flip-Chip Bonding Process

This study assesses the high-temperature storage (HTS) test and the pressure-cooker test (PCT) reliability of an assembly of chips and flexible substrates. After the chips were bonded onto the flexible substrates, specimens were utilized to assess the HTS test and PCT reliability. After the PCT and HTS tests, the die-shear test was applied to examine changes in die-shear forces. The microstructure of the test specimens was analyzed to evaluate reliability and to identify possible failure mechanisms. When the duration of the HTS test was increased, the percentage of gold bumps that peeled off from the surface of the copper pads on the chip side increased, and a crack was present at the bonding interface between the gold bumps and chip bond pads. This crack was due to thermal stress generated during the HTS test, and degraded the die-shear force of the assembly of chips and flexible substrates. After the PCT, the crack was present at the interface between deposited layers of copper electrodes after the specimens were subjected to the PCT for various durations. Moisture penetrated into the deposited layers of the copper electrodes, deposited layers lost their adhesion, and the crack progressed from the corner into the central bond area as the test duration increased. To improve the PCT reliability of assemblies of chips and flexible substrates using the thermosonic flip-chip bonding process, one must prevent moisture from penetrating into deposited layers of copper electrodes and prevent crack formation at the interface between nickel and copper layers. Underfill would be an effective approach to prevent moisture from penetrating into deposited layers during the PCT, thereby improving the reliability of the samples during the PCT.

Intermetallic Compound Growth and Reliability of Cu Pillar Bumps Under Current Stressing

Fine-pitch Cu pillar bumps have been adopted for flip-chip bonding technology. Intermetallic compound (IMC) growth in Cu pillar bumps was investigated as a function of annealing or current stressing by in situ observation. The effect of IMC growth on the mechanical reliability of the Cu pillar bumps was also investigated. It is noteworthy that Sn exhaustion was observed after 240 h of annealing when current stressing was not applied, and IMC growth rates were changed remarkably. As the applied current densities increased, the time required for complete Sn consumption became shorter. In addition, Kirkendall voids, which would be detrimental to the mechanical reliability of Cu pillar bumps, were observed in both Cu3Sn/Cu pillars and Cu3Sn/Cu under-bump metallization interfaces. Die shear force was measured for Cu pillar samples prepared with various annealing times, and degradation of mechanical strength was observed.

Impact of probing procedure on flip chip reliability

Probe-after-bump is the primary probing procedure for flip chip technology, since it does not directly contact the bump pad, and involves a preferred under bump metallurgy (UBM) step coverage on the bump pads. However, the probe-after-bump procedure suffers from low throughputs and high cost. It also delays the yield feedback to the fab, and makes difficult clarification of the accountability of the low yield bumped wafer between the fab and the bumping house. The probe-before-bump procedure can solve these problems, but the probing tips may over-probe or penetrate the bump pads, leading to poor UBM step coverage, due to inadequate probing conditions or poor probing cards. This work examines the impact of probing procedure on flip chip reliability, using printing and electroplating bumpings on aluminum and copper pads. Bump height, bump shear strength, die shear force, UBM step coverage, and reliability testing are used to determine the influence of probing procedure on flip chip reliability. The experimental results reveal that bump quality and reliability test in the probe-before-bump procedure, under adequate probing conditions, differ slightly from the corresponding items in the probe-after-bump procedure. UBM gives superior step coverage of probe marks in both probe-before-bump and probe-after-bump procedures, implying that UBM achieves greater adhesion and barrier function between the solder bump and the bump pad. Both printing and electroplating bump processes slightly influence all evaluated items. The heights of probe marks on the copper pads are 40–60% lower than those on the aluminum pads, indicating that the copper pad enhances UBM step coverage. This finding reveals that adequate probing conditions of the probe-before-bump procedure are suited to sort flip chip wafers and do not significantly affect bump height, bump shear strength, die shear force, or flip chip reliability.