Die Attach Film Research Articles

Development of Dicing Die Attach Film (DDAF) for Small Dies

In recent years, the demand for ever smaller dies including Micro Electro-Mechanical System (MEMS) and sensors is dramatically increasing. Technologies such as automated driving technology are taking off and market pressures to reduce package size and increase the performance in mobile devices are increasing. DDAF increasingly is being utilized in these applications to bond dies to substrates and other dies. DDAF can be used both in the dicing and the die bonding process replacing the need for two separate materials to dice and bond dies. It is composed of DAF (Die Attach Film) and base material, and the DAF layer is what bonds small dies to substrates and other dies. Conventional DDAF however is susceptible to Transfer Failure (TF) with smaller die sizes. It is a failure mode in which the DAF layer peels off from the backside of the die during the die picking up (PU) process. There are multiple root causes for this issue; small dies have small DAF attachment area and smooth die backsides for increased die strength results in an inability of the DAF to anchor itself to the die. However, package reliability was decreased due to the material’s inability to embed itself on to the substrate. Effect factors for suppression of TF with high substrate embedding were explored. To explore these factors a right-angle tear strength method was implemented. Upon analysis of the data a new parameter for the suppression of TF was discovered. This parameter showed a strong correlation to TF. A new DDAF was developed that mitigates TF during PU proess.

Development of all new structure of Dicing Die Attach Film (DDAF) for Stealth Dicing and Cool Expansion processes

Mobile devices, including smart phones and tablets, are increasing in complexity and require ever greater amounts of memory storage. In the past the challenge of higher memory densities and increase functionality has been met through miniaturization of device features, but as we reach the physical limits of feature size, packaging is being relied on more and more to achieve the necessary higher densities in memory and additional device functionality. Thin dies reduce overall package height, however, to achieve high memory densities in low profile packages the die attach material must have an even, thin bond line thickness. DAF (Die Attach Film) is an excellent solution. LINTEC developed an all new DDAF (Dicing Die Attach Film) with thinner DAF for CE (Cool Expansion) process. Conventional tape has a large area of exposed DAF surface which creates the risk of wafer and / or equipment contamination if DAF flies off during the CE process. We developed an all-new tape structure which is compatible with the SD (Stealth Dicing) and CE processes. The structure consists of DAF, IB (Intermediate Basefilm), and dicing tape. The diameter of the DAF and IB is close to the wafer diameter size to significantly reduce the risk of DAF separation and ejection during CE. We considered IB to improve DAF separation and it was found that a thinner IB layer is a good approach to separate DAF effectively. We can adjust adhesion between the DAF and the IB by changing the material properties of the IB, as an effective means to control die-fly and pick-up.

Laser DAF Cut: A Breakthrough Approach of Die Attach Film Singulation for Thin Wafers

Today, semiconductor world is becoming more inclined to thinner Integrated Circuit (IC) packages. IC packages will require thinning of the internal configuration of the package, which involves the die or the wafer and the adhesive material, which is the Die Attach Film (DAF). Aligned to this, as wafers goes thinner it becomes more of a challenge in process development especially during its preparatory stages, such as wafer back grinding and sawing processes. As the die becomes smaller and thinner wafer sawing process should have minimum effect on the mechanical integrity of the silicon so as not to alter its quality.
 New technologies were introduced so as to adopt to this development trend, one of this is the Dicing Before Grinding (DBG). Compared to the normal wafer preparation process that is wafer back grinding before wafer sawing, DBG flow is wafer sawing first prior wafer back grinding processes. The application of DBG technology eliminates the mechanical draw backs of the conventional wafer sawing process. In addition, with the use of DAF for thinner packages, DBG was developed together with the Die Attach Film (DAF) cutting solution, which is Laser DAF Cutting. DAF are separated using Laser as a cutting medium to address potential processability problems that may occur on the conventional mechanical blade saw.
 The paper discuss the Laser DAF cut development that covers the Design of Experiments (DoE) to understand the different characteristics of Laser DAF solution and be validated through actual simulation and wafer processing. The paper will also cover the interaction of different DAF thicknesses and Laser DAF parameters in order to define the critical characteristics so as to understand the behavior of different laser DAF parameters in achieving optimal DAF cutting process responses.

Mechanical Modeling Study on the Impact of Pick-and-Place Design on Die Attach Voids

Pick-and-place (PnP) rubber tip is used for the die attach process in semiconductor packaging. During the die attach process involving a very thin integrated circuit (IC) die, voids in the die attach film (DAF) adhesive were observed. This paper presents the modeling study conducted to understand the impact of PnP rubber tip design on the occurrence of DAF voids. Mechanical modeling was done to simulate the deformation of the very thin die when it is picked using the PnP rubber tip. Different PnP rubber tip designs were modeled. The results revealed that the die deforms during the die pick up process because of the vacuum force, and rubber tip design affects the amount of deformation. It was also found out that more DAF voids occur when the resulting die deformation is larger.

Die Attach Film Bleed out Resolution through Process Optimization on DFN Packages

The development of new technology with thinner and smaller packages has become the movement and focus on semiconductor assembly industry. This paper presents an improvement done in dual-flat no-leads (DFN) package to resolve the quantity of rejection due to die attach film (DAF) bleed out on the die paddle of the leadframe. This reject manifestation was seen after die attach process. Parameter optimization particularly for the bonding with the combination of bond force and bond time parameter was done to eliminate this type of issue after die attach process. With this die attach process optimization and improvement done, DAF bleed out occurrence was eliminated with 100% reduction improvement.

Package Substrate Die Pad Roughening Innovative Solution to Strengthened Die Attach Adhesion

Poor die adhesion to substrate resulting to stray dice issue for the MEMS package was encountered. This die bond failure mechanism has a downstream effect specifically on the mold process. The presence of the stray die resulted to mold compound leakage outside the tool cavity due to planarity not achieved. The mold compound that leaks affected the overall package thickness, thus exposing the wires.
 Using the Design of Experiment methodology, the team generated different simulations and validations to resolve the stray die problem. Based on the simulation and experiments, it was established that an optimum substrate roughness is necessary to achieve a better adhesion between the Die adhesive and the substrate. 
 This paper presents a systematic study on how the substrate roughness can improve the adhesion of Die Attach film (DAF) to the substrate thereby resolving the Stray Die problem. Results showed that the die adhesion strength on the substrate increases as the substrate surface roughness increased from Ra 0.05 um to Ra 1.5 ~ 2.0 mm. Consequently, the rejection rate of stray dice was eliminated. This new learning will be used to establish a standard on surface roughness for substrate-based material that can be applied to new packages.

Effect of Backgrinding Tape Lamination on Die Alignment

The continuing growth and development on semiconductor package miniaturization have become a particular interest and focus semiconductor industry. The importance of thinner packages also demands a thinner vertical structure of the integrated circuit (IC) design with silicon die or the wafer playing essential role in package thinning. As the wafer goes thinner, problems may occur in the wafer preparation or pre-assembly. With the introduction of new wafer preparation technologies such as dicing before grinding and laser die attach film (DAF) cut, technical challenges were inevitable. The paper focused on the effect of backgrinding tape lamination on die alignment. Tensionless lamination helped eliminate the horizontal pressure applied into the tape thus mitigating the die mis-alignment problem. For future works, the configuration could be applied on wafers with similar technology and/or application.

Mitigating Wafer Edge Cut Defect through Tensionless Tape Lamination Technique

Thinner and smaller packages require thinner vertical structure of the integrated circuit (IC) design with the wafer playing essential role in package thinning. As the wafer goes thinner, problems may occur in the pre-assembly or wafer preparation. With the introduction of new pre-assembly technology such as laser die attach film (DAF) cut and dicing before grinding, technical challenges were expected. The paper focused on eliminating the edge cutting issue by considering the appropriate taping lamination technique. Tensionless lamination helped eliminate the horizontal pressure applied into the tape thus mitigating the edge cutting problem. For future works, the configuration shared in this paper could be applied on wafers with comparable technology.

Improved Chuck Table Design for Silicon Wafer Defects Resolution

The paper aimed to mitigate wafer defects such as large kerf shifting issue, dice pop-out occurrence and edge cut defects in the wafer preparation or pre-assembly stage of integrated circuits (IC) assembly manufacturing. With the introduction of new wafer preparation technologies such as dicing before grinding (DBG) and laser die attach film (DAF) cut, technical challenges were encountered. The paper focused on the interaction of different glass chuck table design and laser DAF parameter in order to address the problems. Based on the evaluation and revalidation of results, it has been identified that the single hole without outer groove glass chuck table design improved the response, eliminating dice pop-out issue at laser DAF cut, as well as the kerf shifting issue and edge cut defect.

Critical Insights in the Application of Convection and Pressure Curing in Eliminating DAF Voids

The absent of reliable production controls for Die Attach Film (DAF) voids detection allowed defect escapee for Ball Grid Array (BGA) devices using non-conductive film material leading to gross assembly rejection and customer complaints. This paper presents the evaluation of pressure curing as an alternative to the convection curing in die attach process with additional capability to eliminate the DAF voids on non-conductive films. Through Analysis of Variance (ANOVA) analysis, green peeling test, Scanning Acoustic Microscope (SAM), cross section analysis and reliability test performed between samples arrives to the conclusion that pressure oven has a significant impact in die shear strength improvement and DAF voids elimination with positive response in reliability requirement. The result of the study improves the assembly flow and production control of BGA devices through the transition of convection to pressure curing technology.

Die Attach Assembly Process Tool Advancement

Die attach film (DAF) voids detection is one of the challenges during the introduction of non-conductive adhesives for integrated circuit products affecting production control robustness and detection. In this paper, a specialized tool capable to distinguish and quantify the amount of DAF voids is presented wherein the implementation of semi-auto grid lines generates more precise measurement and correct defect call-out. The tool is proposed as an alternative option for x-ray inspection that is found to be incapable in proper detection and accurate measurement of gaps and un-occupied area within the adhesive thickness that produces over estimation of production rejects.

Laser DAF Cut Augmentation for Thin Wafers

The semiconductor industry is becoming more inclined to thinner integrated circuit (IC) packages. Thinner packages with thin wafer or die prefer the die attach film (DAF) technology as the die adhesive material solution. As the wafer goes thinner, it becomes more of a challenge in process development, especially during its assembly preparatory stages. As the dies become smaller and thinner, wafer sawing process should have minimum effect on the mechanical integrity of the silicon so as not to alter its quality.
 New technologies were developed and introduced in the industry and one of this is the laser die attach film (DAF) cutting. The method was developed together with dies before grinding (DBG) as a cutting medium to address potential processability problems that may occur on the conventional mechanical blade saw. This paper discusses the laser DAF cut development covering the design of experiments (DOE) to understand the different characteristics of laser DAF solution. Validations are made through actual simulation and wafer processing. The paper also covers the interaction of different DAF thicknesses and parameters in order to define the critical characteristics in achieving optimal DAF cutting process responses.

In depth study of lead frame tape residuein quad flat non-leaded package

PurposeLead frame tape is a crucial support for lead frames in the IC assembly process. The tape residue on the quad flat non-leaded (QFN) could result in low reliability and failure in electrical conductivity tests. The tape residue would affect overall performance of the chips and contribute to low pass yield. The purpose of this paper is to present an in-depth study of tape residue and factors that may affect it.Design/methodology/approachAn experiment using lead frame and tapes from three manufacturers with two types of die bond adhesives, namely, die attach film (DAF) and wafer back coating (WBC), was conducted. Copper (Cu) wire bonding and die bonding performances were measured in terms of process capability, stitch bond strength and die attach strength.FindingsResults showed that no tape residue was observed on the thermoplastic adhesive-based lead frames manufactured by Hitachi after the de-taping process because of the tape’s thermoplastic adhesive properties.Originality/valueThis paper studies the occurrence of tape residue and a viable solution for it through the correct process optimization and combination of semiconductor manufacturing materials. Factors that may affect tape residue have also been studied and further research can be done to explore other options in the future as an alternate solution.

Optimization of Elastic Modulus and Cure Characteristics of Composition for Die Attach Film

Optimization of Elastic Modulus and Cure Characteristics of Composition for Die Attach Film

Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging

The design, materials, process, fabrication, and reliability of fan-out wafer-level packaging (FOWLP) with chip-first and die face-up method are investigated in this paper. Emphasis is placed on the issues and their solutions (such as reconstituted carrier, die-attach film placement, pitch compensation, die shift, epoxy molding compound dispensing, compression molding, warpage, and Cu revealing) during the fabrication of a very large test chip (10 mm $\times10$ mm $\times 150\,\,\mu \text{m}$ ) and test package (13.47 mm $\times13.47$ mm), and three redistribution layers with the smallest linewidth/spacing = $5~\mu \text{m}/5~\mu \text{m}$ . The FOWLP test package on a six-layer printed circuit board is subjected to 1000 drops of the shock test with a magnitude = 1500 G/ms. Recommendations of process integration and guidelines on FOWLP with chip-first and die face-up are provided.

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs)

Abstract This study is for fan-out wafer-level packaging (FOWLP) with chip-first (die face-up) formation. The chips with Cu contact-pads on the front-side and a die attach film (DAF) on the backside are picked and placed face-up on a temporary glass wafer carrier with a thin layer of light-to-heat conversion (LTHC) material. It is followed by compression molding with epoxy molding compound (EMC) and post mold cure (PMC) on the reconstituted wafer carrier, and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. Next comes the de-bonding of the carrier with a laser, and then the dicing of the whole reconstituted wafer into individual packages. A 300mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100μm has also been fabricated (a total of 325 test packages on the reconstituted wafer.) This test package has three RDLs; the line width/spacing of the first RDL is 5μm/5μm, of the second RDL is 10μm/10μm, and of the third RDL is 15μm/15μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide (PI) and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

In this paper, the warpage and thermal performances of fan-out wafer-level packaging (FOWLP) are investigated. Emphasis is placed on the characterization of the effects of FOWLP important parameters, such as chip size, chip thickness, package/chip area ratio, epoxy molding compound (EMC), chip EMC cap, reconstituted carrier material and thickness, and die-attach film, on the warpage after postmold cure and backgrinding of the EMC. The simulation results are compared to the experimental measurements. Also, the thermal performance (junction-to-ambient thermal resistance) of FOWLP with various chip thicknesses is characterized. Finally, some FOWLP important parameters affecting the warpage and thermal performances are recommended.

Plasma Dicing Process-Flows for Advanced Packaging Fabrications

Abstract Comprehensive investigations were conducted on identifying integration efforts needed to adapt plasma dicing technology in BEOL pre-production environments. First, the authors identified a few suitable process flows. Within the plasma dicing process flows, laser grooving before plasma etching was shown to be a key unit process to control the resulting die sidewall quality. Significant improvement on laser grooving quality has been demonstrated. Through these efforts, extremely narrow kerfs and near ideal dies strengths were achieved on Si dies. The Bosch-etching based plasma dicing process generates fluorinated polymer residues both on the Si die sidewalls as well as under the topography overhangs on wafer surfaces, such as under the solder balls or micro-bumps. The fluorinated polymers in certain areas cannot be cleaned by an in-chamber post-treatments. Multiple wet chemistry-based cleaning methods demonstrated excellent process capability, and are compatible with plasma singulated dies-on-tape handling. Lastly, many methods exist for backside metal and under Si die-attach-film (DAF) separations. The authors highlighted recent processing results suitable for post-plasma dicing die separations of such film materials.

Characterizations of Fan-out Wafer-Level Packaging

Abstract The calling for smaller form factor, higher I/O density, higher performance and lower cost has made fan-out wafer level packaging (FOWLP) technology the trend. Good control of die position accuracy and molded wafer warpage are some of the keys to achieve high-yield production for FOWLP. In this study, 10mm×10mm test chips were fabricated and attached (chip-first and die face-up) onto 12 inch glass wafer carriers using die-attach-film (DAF). These reconfigured wafers were compression-molded with selected epoxy molding compounds (EMC). Cu bumps (contact-pads) were revealed by grinding, and redistribution layers (RDLs) were fabricated by lithography and electroplating process. The fan-out wafers were evaluated and characterized after each process step with main focus on the die-misplacement/die shift, re-configured wafer warpage, compression molding defects and RDL fabrication defects. The root causes of these defects were investigated and analyzed, while the possible solutions to overcome the defects were proposed and discussed.

Modeling of moisture over-saturation and vapor pressure in die-attach film for stacked-die chip scale packages

Die-attach film failure during soldering reflow is of particular concern for reliability of 3D ultra-thin stacked-die chip scale packages (CSPs), as extremely high vapor pressure can be generated from vaporized moisture to cause severe damages. Under rapid heating, pressure-driven moisture vapor flow could become as significant as concentration-driven diffusion, and should be included in moisture transport models. In this study, a convection–diffusion (CD) model is presented for analyzing vapor pressure and moisture behavior of soft die-attach films for 3D CSPs, with both vapor flow and the effect of temperature on saturated moisture content considered. By using a 1D model according to experimental observations, the over-saturation phenomenon in the thin film and vapor pressure evolution are investigated. It is found that the reflow profiles and substrate thickness could have great impact on the magnitude of vapor pressure, which agrees well with the experimental results. Sensitivity analyses show that a high vapor permeability and a large porosity could lead to low vapor pressure. Being a vapor pressure-based model, the CD model is suitable to study multiple-material systems without discontinuity issue at the material boundary. It is concluded that the CD model could serve as an effective method for predicting vapor pressure and moisture behaviors during soldering reflow for 3D stacked-die CSPs.