Abstract
Abstract The calling for smaller form factor, higher I/O density, higher performance and lower cost has made fan-out wafer level packaging (FOWLP) technology the trend. Good control of die position accuracy and molded wafer warpage are some of the keys to achieve high-yield production for FOWLP. In this study, 10mm×10mm test chips were fabricated and attached (chip-first and die face-up) onto 12 inch glass wafer carriers using die-attach-film (DAF). These reconfigured wafers were compression-molded with selected epoxy molding compounds (EMC). Cu bumps (contact-pads) were revealed by grinding, and redistribution layers (RDLs) were fabricated by lithography and electroplating process. The fan-out wafers were evaluated and characterized after each process step with main focus on the die-misplacement/die shift, re-configured wafer warpage, compression molding defects and RDL fabrication defects. The root causes of these defects were investigated and analyzed, while the possible solutions to overcome the defects were proposed and discussed.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
