Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging

Abstract

The design, materials, process, fabrication, and reliability of fan-out wafer-level packaging (FOWLP) with chip-first and die face-up method are investigated in this paper. Emphasis is placed on the issues and their solutions (such as reconstituted carrier, die-attach film placement, pitch compensation, die shift, epoxy molding compound dispensing, compression molding, warpage, and Cu revealing) during the fabrication of a very large test chip (10 mm $\times10$ mm $\times 150\,\,\mu \text{m}$ ) and test package (13.47 mm $\times13.47$ mm), and three redistribution layers with the smallest linewidth/spacing = $5~\mu \text{m}/5~\mu \text{m}$ . The FOWLP test package on a six-layer printed circuit board is subjected to 1000 drops of the shock test with a magnitude = 1500 G/ms. Recommendations of process integration and guidelines on FOWLP with chip-first and die face-up are provided.