Physical Device Simulation Research Articles

Investigation of Thermal Properties in Fabricated 4H-SiC High-Power Bipolar Transistors

Silicon Carbide bipolar junction transistors have been fabricated and investigated. The transistors had a maximmn current gain of approximately 10 times, and a breakdown voltage of up to 600 V. When operated at high power densities the device showed a clear self-heating effect, decreasing the current gain. The junction temperature was extracted during self-heating to approximately 150 °C, using the assumption that the current gain only depends on temperature. Thermal images of a device under operation were also recorded using an infrared camera, showing a significant temperature increase in the vicinity of the device. Physical device simulations have been used to analyze the measured data. The thermal conductivity is fitted to model the measured self-heating, and the lifetime in the base is fitted against the measurement of the current gain.

Ge-profile design for improved linearity of SiGe double HBTs

The influence of Ge-profile design on SiGe HBT linearity-harmonic distortion has been quantified using finite element physical device simulation. It was demonstrated that proper Ge-profile tailoring allows the linearity to be improved for both low- and high-current operation. High injection heterojunction barrier effects are shown to have a significant influence on the higher order harmonics. The influence of the Ge-profile design on linearity was found to be comparable to the influence from the epitaxial collector doping profile.

Accurate analytical delay expression for short channel CMOS SOI inverter using Monte Carlo simulation

This paper reports on an analysis of propagation delay τ D for deep sub-micron CMOS/SOI inverters. We derive simple propagation delay expressions for step and ramp inputs, using Monte Carlo simulation. These expressions consist of linear combinations of time constants. As a physical device simulation tool, the Monte Carlo method is well adapted to such a study, since it does not require any analytical model of electrical device parameters. The validity of the above expressions is critically checked via Monte Carlo simulation of a wide range of inverters under various load conditions. The discrepancy between calculated and simulated propagation delay is less than 10%.

Numerical simulation of the generation of gain switched laser pulses

Gain switched laser pulses with FWHM of 32 ps having an optical peak power exceeding 400 W are generated using low cost single heterostructure (SH) Fabry–Perot laser diodes. To examine and to optimize this effect in detail, a thorough physical device simulation is done. Maxwell's equations together with a simplified version of the Boltzmann transport equation (BTE) and various parameters like carrier recombination and material gain, form a coupled set of nonlinear, inhomogeneous partial differential equations, that are discretized using the finite difference scheme and solved selfconsistently.

Mechanisms for output power expansion and degradation of PHEMT's during high-efficiency operation

PHEMT stability in high efficiency power amplifiers (where the PHEMT is typically driven into reverse gate-drain breakdown) has been examined under accelerated dc stresses. Such stresses initially caused a slight increase in drain current and decrease in threshold voltage due to hot-carrier injection into the buffer which was not seen in similarly stressed MESFET's. On the other hand, continued stressing resulted in significant decrease in drain current and increase in drain resistance due to hot-carrier injection into the surface passivation which is consistent with the typical MESFET degradation mode. The degradation rate of PHEMT's is approximately two orders of magnitude faster than that of MESFET's. Two-dimensional physical device simulation confirms that the faster degradation of PHEMT's is due to their higher sensitivity to surface conditions.

An accurate large-signal physical model for microwave GaAs/AlGaAs HBTs

This article describes, for the first time, the development of a two-dimensional physical model which accurately characterizes the DC, bias dependent small-signal, and large-signal power characteristics of GaAs/AlGaAs HBTs. This model is implemented using a commercial physical device simulator. It is shown that the physical model can accurately predict the output power, gain, and efficiency of GaAs HBTs, even well into compression where device nonlinearities are significant. A complete description of the model is provided including a discussion of the relevant physical processes, the simulation device geometry, the appropriate material parameters, and the methods for scaling to multifinger devices. © 1996 John Wiley & Sons, Inc.

Accurate base and collector current modeling of polysilicon emitter bipolar transistors: Quantification of hole surface recombination velocity

We present predictive and accurate modeling of base and collector currents in poly-Si emitter bipolar transistors Ref. . Using a standard 0.8 μm bipolar complementary metal–oxide–semiconductor technology process flow Ref. , numerous experiments are performed. The base and emitter doping profiles are varied intentionally over a wide range in a controlled manner, so as to extract a self-consistent set of apparent band-gap narrowing, minority-carrier mobility, intrinsic concentration parameter, and Auger recombination rate that is valid for simultaneously modeling bipolar transistor base and collector currents. The standard nature of the fabrication process technology chosen for this study allows the results to be more generally applicable. The doping concentrations for physical device simulations are taken directly from secondary-ion-mass spectrometry measurements. These profiles are then verified using spreading resistance measurements and capacitance–voltage measurements. It is shown that the measured base and collector currents for all experiments at room temperature can be fit simultaneously using Klaasen’s unified apparent band-gap narrowing and mobility model Ref. . The emitter poly-Si/epi-Si interface (surface) hole recombination velocity is derived as a function of the emitter implant dose (arsenic concentration in the emitter) consistent with the model mentioned above. Sensitivity of the simulation results to model parameters is shown. It is further shown that the emitter implant dose can be used as a bipolar transistor optimization parameter.

Predictive worst case statistical modeling of 0.8- mu m BICMOS bipolar transistors: a methodology based on process and mixed device/circuit level simulators

The authors discuss the use of mixed-level physics-based device/circuit simulation software and semiconductor process simulator in the construction of predictive worst case process conditions for bipolar transistors currently being manufactured in AT&T 0.8- mu m BICMOS technology. Process fluctuations are introduced into the process simulator using the Latin hypercube (Monte Carlo) sampling method. The method is different from those in previous similar studies in that the compact device model parameter extraction step for each sample process is bypassed and active devices in the circuit are described by the physical device simulator rather than a compact model representation. This eliminates deficiencies associated with compact semiconductor device models. Furthermore, inaccuracies and difficulties introduced by compact model parameter extractions (especially for bipolar transistors) are also eliminated. The method is very useful in identifying critical process steps which determine the electrical performance of the devices and circuits.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A study on the physical mechanism in the recovery of gate capacitance to C/sub ox/ in implanted polysilicon MOS structures

The anomalous CV characteristics of MOS capacitor structures with implanted n/sup +/ polysilicon gate and p-type silicon substrate are studied through physical device simulation and experimental characterization over a wide range of frequencies and temperatures ranging from 100 to 250 K. It is shown that this anomalous CV behavior can be fully explained by the depletion of electrons and the formation of a hole inversion layer in the polysilicon gate due to energy band bending. The use of transistor structures for characterizing the polysilicon gate electrode is proposed. The results suggest thermal generation rather than impact ionization to be the dominant physical mechanism in supplying holes required by the inversion layer at the polysilicon-SiO/sub 2/ interface. This result also implies that hot-hole injection from the polysilicon gate into the SiO/sub 2/ gate dielectric should not present a serious problem in device reliability. >

Physical device simulation in a shrinking world

The effect of shrinking device dimensions from micrometers to nanometers on the validity of device simulators is examined. It is shown that the assumptions underlying the drift-diffusion equation weaken when applied to small devices. Using the Monte Carlo method to simulate the microscopic motion of several thousand carriers as they travel through a device, an alternative approach that is beginning to find wide application in device engineering is discussed. Because the Monte Carlo method directly mimics carrier motion at a microscopic level, it provides highly accurate, detailed, realistic simulations of carrier transport in devices. However, it imposes a heavy computational burden, and the noise associated with the use of a relatively small sample-a few thousand electrons-sometimes limits its application. Nevertheless, its advantages continue to grow as device dimensions shrink. As the devices shrink to dimensions below 100 nm, the wave nature of electrons will play an increasingly important role, and even semiclassical Monte Carlo techniques are inadequate. Quantum approaches for use in that regime are considered. >

Physical modeling of GaAs MESFETs in an integrated CAD environment: from device technology to microwave circuit performance

The linkage between a physical device simulator for small- and large-signal characterization and CAD (computer-aided design) tools for both linear and nonlinear circuit analysis and design is considered. Efficient techniques for the physical DC and small-signal analysis of MESFETs are presented. The problem of physical simulation in a circuit environment is discussed, and it is shown how such a simulation makes possible small-signal models accounting for propagation and external parasitics. Efficient solutions for physical large-signal simulation, based on deriving large-signal equivalent circuits from small-signal analyses under different bias conditions, are proposed. The small- and large-signal characterizations allow physical simulation to be performed efficiently in a circuit environment. Examples and results are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A large-signal physical MESFET model for computer-aided design and its applications

A quasi-static, large-signal MESFET circuit model is presented. It is based on a comprehensive quasi-two-dimensional, semiclassical, physical device simulation, and its unique formulation and efficiency make it suitable for the computer-aided design of nonlinear MESFET subsystems. Using this approach the semiconductor equations are reduced to a consistent one-dimensional approximation requiring substantially less computing resources than a full two-dimensional simulation. CPU time is typically reduced by a factor of 1000. A single/two-tone harmonic balance analysis procedure which uses the describing frequency concept is also developed and combined with the MESFET model. Numerical load-pull contours as well as intermodulation distortion contours have been simulated; their comparison with measured results validates the approach taken. >

Circuit modeling of collector current spreading effects in quasi-saturation for advanced bipolar transistors

The advanced bipolar transistor operating in the quasi-saturation region has been modeled, including collector current spreading effects. It is shown that the multidimensional collector current spreading, resulting from high carrier concentration gradient in the collector, ameliorates quasi-saturation effects in the d.c. and transient operation. The mechanism of collector spreading is investigated by physical device simulations. SPICE circuit simulations employing the collector spreading model are compared with measurements and are found to be in excellent agreement.