Abstract
The anomalous CV characteristics of MOS capacitor structures with implanted n/sup +/ polysilicon gate and p-type silicon substrate are studied through physical device simulation and experimental characterization over a wide range of frequencies and temperatures ranging from 100 to 250 K. It is shown that this anomalous CV behavior can be fully explained by the depletion of electrons and the formation of a hole inversion layer in the polysilicon gate due to energy band bending. The use of transistor structures for characterizing the polysilicon gate electrode is proposed. The results suggest thermal generation rather than impact ionization to be the dominant physical mechanism in supplying holes required by the inversion layer at the polysilicon-SiO/sub 2/ interface. This result also implies that hot-hole injection from the polysilicon gate into the SiO/sub 2/ gate dielectric should not present a serious problem in device reliability. >
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