Device Mismatch Research Articles

Background DAC Error Estimation Using a Pseudo Random Noise Based Correlation Technique for Sigma-Delta Analog-to-Digital Converters

This paper presents a new approach for estimating non-idealities in unit element feedback digital-to-analog converters of Sigma-Delta analog-to-digital converters. The presented method involves a background correlation technique to determine static and dynamic device mismatches causing linear time-invariant errors of the unit cells, as well as a way to digitally correct a modulator's output. Simulations show that the method can be used to precisely estimate imperfections and improve non-ideal modulators up to their ideal resolution, independent from the chosen oversampling ratio or architecture. The method is defined mathematically and verified by simulations. Comparisons with a common dynamic element matching technique show its superior behavior especially for low oversampling ratios.

Development of rugged 2 GHz power bars delivering more than 100 W and 60% power added efficiency

AbstractIn this work we systematically study the structural, optical and electrical properties of AlGaN/GaN heterostructures grown by MOCVD 3‐inch on SiC substrates The finally developed HEMTs demonstrate excellent high‐voltage stability, high power performance and large power added efficiencies. For a drain bias of 100 V an output‐power‐density around 26 W/mm with 25 dB linear gain is obtained. On 36 mm gate width devices an output power beyond 100 W is achieved with a power added efficiency above 60% and a linear gain around 17 dB. Ruggedness on these large devices is proven by successfully passing harsh intentional device mismatch tests during operation at 50 V. Reliability is tested at a drain bias of 50 V. Under DC conditions a drain‐current degradation below 20% after 20 years is extrapolated. Under RF stress the observed change in output power is well below 0.1 dB after a test duration of more than 500 h. (© 2010 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

CONTINUATION ANALYSIS OF A PHASE/QUADRATURE ELECTRONIC OSCILLATOR

An RF phase-quadrature oscillator is analyzed. The designer "ensured" the phase-quadrature working condition through a suitable cross-coupled electrical connection between the two parts composing the complete oscillator. Through a detailed analysis of the dynamics of this oscillator, we show that device mismatch can lead to an unexpected stable working mode where the oscillator does not operate in a phase-quadrature condition. The proposed analysis has been first performed on a simplified model of the oscillator to allow the use of software packages for numerical continuation. The results of the analysis of the simplified oscillator dynamics have been then checked by means of accurate device models from a 65 nm RF technology library.

A Fully Integrated Transmitter with Embedded Antenna for On-Wafer Wireless Testing

This paper presents a fully integrated transmitter with embedded on-chip antennas to demonstrate on-wafer wireless testing. First, on-chip antenna characterization methods based on the measured transmission link gain are described. From the measured transmission link gain, the on-chip antenna gain is determined using the known transmitter gain, a path loss, and an off-chip antenna gain. The proposed two-step method utilizes a high-gain off-chip antenna transmission link for base line calibration data to obtain better gain accuracy. For wireless testing, a fully integrated a 1.2-GHz Hartley image-reject transmitter is implemented in an 40-GHz f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> InGaP/GaAs HBT process. The image rejection (IR) ratio is measured to demonstrate process control monitoring of device mismatches. Both dipole and loop antennas are integrated to study their radiation efficiency as their dimensions are much less than the wavelength. The loop antenna provides about 7 dB better transmission gain. The IR ratio is measured wirelessly from a number of samples to monitor the die-to-die variations in the in-phase/quadrature mismatch. Monte Carlo simulations are used to aid the analysis of the sources of amplitude and phase mismatches.

Improvement of Poly-Pimple-Induced Device Mismatch on 6T-SRAM at 65-nm CMOS Technology

An incremental poly etching method can improve the poly pimple defect-induced device mismatch on the static noise margin (SNM) of 65-nm-node low-power 6T-SRAM. The improvement on circuit level is examined by the yield of scan chain and memory built-in self-test (MBIST), which is known to correlate well to process-induced defects.

A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture

We have developed a 6b 2.7 GS/s folding ADC with on-chip background self-calibration in 90 nm CMOS technology. The ADC achieves high-speed operation of 2.7 GS/s at low power consumption of 50 mW from a 1.0 V power supply and the figure of merit (FOM) is 0.47 pJ/conversion-step. The key technique is a digital background self-calibration architecture which compensates for the large mismatch of small devices in the ADC and also corrects the ADC characteristics degradation during operation due to the drift of environmental factors such as temperature. This background calibration technique suited for multi-GHz operation is realized by two-channel ADC architecture and digital smoothing technique, which uses averaging of two comparator offsets and reconfiguration of reference connection. To minimize the power dissipation, a cascade-calibrated folding-interpolating architecture has been developed. It reduces the overall analog power of our design by 50%, compared with a conventional architecture which applies calibration only to preamplifiers. By utilizing these low-power techniques, we have successfully developed a low-power ADC with all functions including the background self-calibration control circuit.

Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary metal oxide semiconductor technology

Shallow trench isolation (STI) induced mechanical stress affects the device behavior in the advanced complementary metal oxide semiconductor (CMOS) technology. This article presents how to use an optimal STI process to reduce transistor mismatch and leakage current induced standby current in static random access memory (SRAM). The STI induced mechanical stress affects the device behavior in the advanced CMOS technology. The optimized STI process can reduce junction and bulk leakage that occurs on the STI sidewall due to STI compressive stress enhancing boron diffusion and increasing junction electric field of STI sidewall resulting in band-to-band-tunneling (BTBT) degradation. An obvious decrease in BTBT occurs on STI edge sidewall that is observed by using the optimized STI process. Meanwhile, the optimized STI process has better length of diffusion effect. Moreover, the optimized STI process can improve the parasitic device at STI edge because of smaller divot. Since random fluctuation of channel dopant and process induced device mismatch are major considerations in SRAM cell, we examine STI sidewall boron dopant diffusion effect on SRAM due to BTBT increasing exponentially with increasing doping concentration in the P-well of negative metal oxide semiconductor field effect transistor. The mismatch of passing gate of SRAM and Vcc_min can also be improved by leakage reduction from the optimized STI process due to improved random dopant fluctuation.

Calibration and Characterization of Self-Powered Floating-Gate Usage Monitor With Single Electron per Second Operational Limit

Self-powered monitoring refers to a signal processing technique where the computational power is harvested directly from the signal being monitored. In this paper, we present the design and calibration of a CMOS event counter for long-term, self-powered mechanical usage monitoring. The counter exploits a log-linear response of the hot-electron injection process on a floating-gate transistor when biased in weak-inversion. By configuring an array of floating-gate injectors to respond to different amplitude levels of the input signal, a complete analog processor has been designed that implements a level counting algorithm, which is widely used in mechanical usage monitoring. Measured results from a fabricated prototype in a 0.5-?m CMOS process demonstrate that the processor can sense, store and compute over 105 usage cycles with an injection limit approaching one single electron per second and with a counting resolution of 5 bits. This paper also presents a calibration algorithm that is used for compensating the variations which arise due to device mismatch, power supply and temperature fluctuations. The maximum current rating of the fabricated analog processor has been measured to be less than 160 nA making it ideal for practical self-powered sensing applications.

ABRM: Adaptive $ \beta$-Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling

Subthreshold operation of digital circuits has emerged as a promising approach to achieve ultralow power dissipation. However, extensive application of subthreshold logic is limited due to low performance and high susceptibility to process variation (PV). This paper proposes a PV-tolerant ultradynamic voltage scaling (UDVS) system where performance requirements dictate whether the devices will work in the subthreshold or superthreshold region. Due to different mechanisms of current conduction, it is necessary to use different <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P/N</i> ratios for different regions of operation to improve circuit robustness, performance, and power. With an analytical model of circuit robustness, we present an adaptive body-biasing technique to dynamically adjust the ß-ratio depending on the operating region. Measurements show that our methodology improves the dynamic range of operation the circuits-from 1.2 V all the way down to 85 mV consuming 40 nW (at 85 mV) of power for an 8 × 8 finite-impulse response filter fabricated in a 0.13-¿m technology, and can salvage circuits which otherwise would fail to operate due to device mismatches and skewed <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P/N</i> ratios.

Embedded analogue nonvolatile memory with feedback-controlled programming circuit on-chip

An analogue nonvolatile memory is presented, which is not only CMOS-compatible but also capable of storing analogue currents with a resolution of more than eight bits. The programming process is controlled by a hysteretic comparator on-chip, which stops the injection current automatically by negative feedback, regardless of the programming nonlinearity and device mismatches. With the simple, on-chip programming circuit, the proposed analogue memory is capable of storing currents ranging from 1 to 18 μA accurately with negligible variations across different memory cells.

Criterion to Evaluate Input-Offset Voltage of a Latch-Type Sense Amplifier

In advanced CMOS technologies where device mismatches are of major reliability concern, predicting the input-offset voltage of the sensing circuit is a crucial step in the design process as it has a direct impact on the yield. This work uses the Taylor expansion to derive a criterion to evaluate input-offset voltage of a latch-type voltage-mode sense amplifier. By innovatively setting the correct sensing criterion, this method provides a very simple, yet accurate and robust model to quantify the input-offset of the sense amplifier. The resulting offset expression incorporates three types of device mismatches, namely the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ), the trans-conductance ( K = ¿C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0x</sub> W/L) and the capacitance (C). The model is then analyzed under the worst-case scenario. It is shown that V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> has the greatest influence on the offset voltage, followed by K and C mismatches. Second-order approximation is also considered when high-level mismatches are present. Extensive simulations have also been carried out to verify the accuracy of the model using three different CMOS technologies.

Linearised charge pump independent of current mismatch through timing rearrangement

In conventional fractional N phase-locked loops (PLLs), charge pump nonlinearity dominates the overall loop linearity. A nonlinear charge pump increases close-in phase noise and fractional spur. Charge pump nonlinearity is mainly caused by up and down current mismatch which is in turn caused by device mismatch, and finite output impedance. A new charge pump linearisation technique is proposed by introducing an extra delay in the phase-frequency detector (PFD), so that charge nonlinearity caused by current mismatch is cancelled. The new method is independent of current mismatch. A fractional N PLL has been implemented in a 0.18 µm CMOS technology with the proposed linearisation technique. The measured fractional spur at 300 kHz offset is −77 dBc at 3.975 GHz.

CMOS Proportional-to-Absolute Temperature Current Reference for Low Voltage Operation

A CMOS Proportional-to-Absolute Temperature current reference for low voltage operation is presented. The proposed circuit can work with supply voltages as low as 1.1 V. The circuit is designed in 90 nm CMOS technology for 2.2 μA reference current at typical corner, 27 C, 1.2 V. It has been extensively simulated across all possible combinations of MOSFET, Resistor, BJT, supply voltage and temperature variation corners. Simulation results have been given for a wide temperature variation from ―40 C to 125 C and supply voltage variation from 1.1 V to 1.3 V. Extensive Monte-Carlo mismatch simulation results show that the circuit is quite robust to the device mismatch yielding low variation in the output reference current.

A 6-bit 2.5-GS/s flash ADC using comparator redundancy for low power in 90 nm CMOS

A 2.5 GS/s flash ADC, fabricated in 90 nm CMOS utilizes comparator redundancy to avoid traditional power, speed and accuracy trade-offs. The redundancy removes the need to control comparator offsets, allowing the large process-variation induced mismatch of small devices in nanometer technologies. This enables the use of small-sized, ultra-low-power comparators with clock-gating capabilities in order to reduce the power dissipation. The chosen calibration method enables an overall low-power solution and measurement results show that the ADC dissipates 30 mW at 1.2 V. With 63 comparators, the ADC achieves 3.9 effective number of bits.

An 8$\times$8 Cell Analog Order-Statistic-Filter Array With Asynchronous Grayscale Morphology in 0.13-$\mu{\hbox{m}}$ CMOS

This paper presents an integrated 8 times 8 cell image processor array demonstrating the parallel implementation of analog order-statistic filtering and grayscale mathematical morphology. Each cell, connected locally to four nearest neighbors and sized 30 times 28 mum2, includes a digitally programmable five-input analog current-mode ranked-order filter. The array also demonstrates an implementation of asynchronously propagating morphological grayscale reconstruction, which is robust against device mismatch. The measurement results of all programmable order-statistic operations are shown, verifying the correct operation of the array. The chip was manufactured in a 0.13- mum 1-poly 6-metal CMOS technology and operates from a single 1.3-V power supply.

Piecewise linear second moment statistical simulation of ICs affected by non‐linear statistical effects

AbstractThis paper presents a methodology for statistical simulation of non‐linear integrated circuits affected by device mismatch. This simulation technique is aimed at helping designers maximize yield, since it can be orders of magnitude faster than other readily available methods, e.g. Monte Carlo. Statistical analysis is performed by modeling the electrical effects of tolerances by means of stochastic current or voltage sources, which depend on both device geometry and position across the die. They alter the behavior of both linear and non‐linear components according to stochastic device models, which reflect the statistical properties of circuit devices up to the second order (i.e. covariance functions). DC, AC, and transient analyses are performed by means of the stochastic modified nodal analysis, using a piecewise linear stochastic technique with respect to the stochastic sources, around a few automatically selected points. Several experimental results on significant circuits, encompassing both the analog and the digital domains, prove the effectiveness of the proposed method. Copyright © 2009 John Wiley &amp; Sons, Ltd.

Time-Dependent Variability Related to BTI Effects in MOSFETs: Impact on CMOS Differential Amplifiers

With the continuous transistor scaling, device mismatch related to intrinsic process variability increases and becomes one of the most important problems to be faced during circuit design. In addition, gate oxide wear-out strongly affects the device reliability and adds a time dependence to device mismatch. In this paper, the impact on circuit functionality of both process variability and gate oxide degradation is studied. First, the effect of the gate oxide damage on the NMOS and PMOS transistor characteristics and their variability has been analyzed. Second, a methodology based on combined SPICE and Monte Carlo simulations to analyze the time-dependent variability at device and circuit levels is presented, which has allowed to reproduce the experimental data. Finally, using the proposed methodology, the influence of the process variability and gate oxide wear-out on the functionality of different configurations of an amplifier circuit was investigated. The results show that both aspects can be decisive in the circuit reliability.

Digitally Programmable Analogue Circuits for Sensor Conditioning Systems

This work presents two current-mode integrated circuits designed for sensor signal preprocessing in embedded systems. The proposed circuits have been designed to provide good signal transfer and fulfill their function, while minimizing the load effects due to building complex conditioning architectures. The processing architecture based on the proposed building blocks can be reconfigured through digital programmability. Thus, sensor useful range can be expanded, changes in the sensor operation can be compensated for and furthermore, undesirable effects such as device mismatching and undesired physical magnitudes sensor sensibilities are reduced. The circuits were integrated using a 0.35 μm standard CMOS process. Experimental measurements, load effects and a study of two different tuning strategies are presented. From these results, system performance is tested in an application which entails extending the linear range of a magneto-resistive sensor. Circuit area, average power consumption and programmability features allow these circuits to be included in embedded sensing systems as a part of the analogue conditioning components.

A Low Power 6-bit Flash ADC With Reference Voltage and Common-Mode Calibration

In this paper, a low power 6-bit ADC that uses reference voltage and common-mode calibration is presented. A method for adjusting the differential and common-mode reference voltages used by the ADC to improve its linearity is described. Power dissipation is reduced by using small device sizes in the ADC and relying on calibration to cancel the large non-ideal offsets due to device mismatches. The ADC occupies 0.13 mm2 in 65 nm CMOS and dissipates 12 mW at a sample rate of 800 MS/s from a 1.2 V supply.

A Comprehensive Investigation of Analog Performance for Uniaxial Strained PMOSFETs

This paper presents a comprehensive investigation of the analog performance for uniaxial strained PMOSFETs with sub -100 nm gate length. Through a comparison between co-processed strained and unstrained devices regarding important analog metrics such as transconductance to drain current ratio ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ), dc gain, linearity, low-frequency noise, and device mismatch, the impact of process-induced uniaxial strain on the analog performance of MOS devices has been assessed and analyzed. Our results indicate that, although the drain current noise spectral density and drain current mismatch of the strained device under low gate voltage overdrive are increased because of the larger gate-bias sensitivity of carrier mobility, the strained device has almost the same low frequency and mismatch performance as the unstrained one at a given <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> . This paper may provide insights for analog design using advanced strained devices.