Device Mismatch Research Articles

Low Power, CMOS-MoS2 Memtransistor based Neuromorphic Hybrid Architecture for Wake-Up Systems

Neuromorphic architectures have become essential building blocks for next-generation computational systems, where intelligence is embedded directly onto low power, small area, and computationally efficient hardware devices. In such devices, realization of neural algorithms requires storage of weights in digital memories, which is a bottleneck in terms of power and area. We hereby propose a biologically inspired low power, hybrid architectural framework for wake-up systems. This architecture utilizes our novel high-performance, ultra-low power molybdenum disulphide (MoS2) based two-dimensional synaptic memtransistor as an analogue memory. Furthermore, it exploits random device mismatches to implement the population coding scheme. Power consumption per CMOS neuron block was found to be 3 nw in the 65 nm process technology, while the energy consumption per cycle was 0.3 pJ for potentiation and 20 pJ for depression cycles of the synaptic device. The proposed framework was demonstrated for classification and regression tasks, using both off-chip and simplified on-chip sign-based learning techniques.

Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC

A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is presented in this paper. This circuit has an advantage of digital circuit concept and can be easily migrated to lower technologies. Also, the digital circuits are less sensitive to the noise and device mismatches can be synthesized and auto place and route (P&R) using EDA tools. The design of the proposed comparator is based on the standard cells implementation. As the proof of concept this comparator is implemented on Xilinx Basys-3 Artix-7 FPGA kit. The prototype of complete 4-bit Flash ADC is designed in 180[Formula: see text]nm CMOS technology with 1.8[Formula: see text]V supply voltage. The measured values of ENOB, SNDR, SNR and SFDR are 3.6, 23.43[Formula: see text]dB, 25.2[Formula: see text]dB and 30.1[Formula: see text]dB, respectively at 33.20[Formula: see text]MHz input frequency and 200[Formula: see text]MHz clock frequency. The total power consumed by the 4-bit flash ADC is 2.14[Formula: see text]mW. The calculated value of DNL and INL is [Formula: see text] LSB and [Formula: see text] LSB respectively.

A Neuromorphic Computational Primitive for Robust Context-Dependent Decision Making and Context-Dependent Stochastic Computation

The prefrontal cortex (PFC) plays an important role in complex cognitive computations, including planning and decision making. Although recurrent spiking neural network (SNN) software models of PFC have been successful in reproducing many of its cognitive computational aspects, little attention has been devoted to the question of how such systems can perform with low-resolution parameters and be robust to noise and variability in their input signals and state variables. Here, we present a mixed-signal analog/digital neuromorphic implementation of a state-dependent SNN architecture that addresses these issues by construction. The network relies on synaptic dis-inhibition to ensure robust decision making even in the face of very large variability. Depending on its connectivity, the network can either perform robustly in a deterministic way or exploit the device mismatch and noise to explore stochastically multiple states in constraint satisfaction problems (CSPs). We validate the architecture by mapping it onto a network of spiking neurons in a multi-core mixed-signal neuromorphic system and presenting experimental results for three different examples of CSPs.

Error-Feedback Mismatch Error Shaping for High-Resolution Data Converters

Device mismatch is a key concern for high-resolution data converters. This paper presents a comprehensive study of the error-feedback (EF)-based mismatch error shaping (MES) technique. EF MES overcomes the key challenge of the classic dynamic element matching-based MES whose complexity grows exponentially with the number of bits; however, the prior EF MES comes with the limitations of limited shaping capability and reduced dynamic range. This paper demonstrates how to perform more advanced EF MES for various types of data converters. Moreover, this paper also proposes the use of digital prediction to address the dynamic range loss issue.

Reducing the Device Delay Mismatch Can Improve Sound Localization in Bimodal Cochlear Implant/Hearing-Aid Users.

In users of a cochlear implant (CI) together with a contralateral hearing aid (HA), so-called bimodal listeners, differences in processing latencies between digital HA and CI up to 9 ms constantly superimpose interaural time differences. In the present study, the effect of this device delay mismatch on sound localization accuracy was investigated. For this purpose, localization accuracy in the frontal horizontal plane was measured with the original and minimized device delay mismatch. The reduction was achieved by delaying the CI stimulation according to the delay of the individually worn HA. For this, a portable, programmable, battery-powered delay line based on a ring buffer running on a microcontroller was designed and assembled. After an acclimatization period to the delayed CI stimulation of 1 hr, the nine bimodal study participants showed a highly significant improvement in localization accuracy of 11.6% compared with the everyday situation without the delay line (p < .01). Concluding, delaying CI stimulation to minimize the device delay mismatch seems to be a promising method to increase sound localization accuracy in bimodal listeners.

The Analysis and Suppressing of Non-Uniformity in a High-Speed Spike-Based Image Sensor.

In this paper, the non-ideal factors, which include spatial noise and temporal noise, are analyzed and suppressed in the high-speed spike-based image sensor, which combines the high-speed scanning sequential format with the method that uses the interspike time interval to indicate the scene information. In this imager, spatial noise contains device mismatch, which results in photo response non-uniformity (PRNU) and the non-uniformity of dark current. By multiplying the measured coefficient matrix the photo response non-uniformity is suppressed, and the non-uniformity of dark current is suppressed by correcting the interspike time interval based on the time interval of dark current. The temporal noise is composed of the shot noise and thermal noise. This kind of noise can be eliminated when using the spike frequency to restore the image. The experimental results show that, based on the spike frequency method, the standard deviation of the image decreases from 18.4792 to 0.5683 in the uniform bright light by using the calibration algorithm. While in the relatively uniform dark condition, the standard deviation decreases from 1.5812 to 0.4516. Based on interspike time interval method, because of time mismatch and temporal noise, the standard deviation of the image changes from 27.4252 to 27.4977 in the uniform bright light by using the calibration algorithm. While in the uniform dark condition, the standard deviation decreases from 2.361 to 0.3678.

A 213-nW/Channel Analog Euclidian Vector Normalizer

This brief presents a novel low-power analog Euclidian vector normalizer for analog signal processing in vector forms, such as the preprocessing of sensor array signals. Instead of using multiple stages of translinear circuits to synthesize the Euclidian norm with square root, squared sum, and division functions, this circuit performs concurrent Euclidian vector normalization on input signals with a feedback control loop to achieve a compact area and low power consumption. A simple two-step calibration is also provided to overcome device mismatches. This 6-channel normalizer is part of an analog gas sensing front end and was implemented in a 65-nm low-power CMOS technology with an area of 0.053 mm2. It consumes a maximum current of $2.08~{\mu }\text{A}$ from 0.6/0.65-V supplies with a response time of 6.5 ${\mu }\text{s}$ , thus achieving a low energy per operation of 1.39 pJ/channel.

PV-Aware Analog Sizing for Robust Analog Layout Retargeting with Optical Proximity Correction

For analog integrated circuits (ICs) in nanometer technology nodes, process variation (PV) induced by lithography may not only cause serious wafer pattern distortion, but also result in device mismatch, which can readily ruin circuit performance. Although the conventional optical proximity correction (OPC) operations can effectively improve the wafer image fidelity, an analog circuit without robust device sizes is still highly vulnerable to such a mismatch effect. In this article, a PV-aware sizing-inclusive analog layout retargeting framework, which encloses an efficient hybrid OPC scheme for yield enhancement, is proposed. The device sizes are tuned during the layout retargeting process by using a deterministic circuit-sizing algorithm considering PV conditions. Our hybrid OPC method combines global rule-based OPC with local model-based OPC functions to boost the wafer image quality improvement but without degrading the computational efficiency. The experimental results show that our proposed framework can achieve the best wafer image quality and circuit performance preservation compared to any other alternative approaches.

High performance CMOS level up shifter with full–scale 1.2 V output voltage

This paper introduces a very low static current CMOS level up shifter for low voltage single supply and high performance. The proposed low to high voltage level shifter is implemented using low threshold voltage transistors in 65 nm CMOS technology and based on differential topology. The shifter circuit was designed to be functional for an input voltage from 0.45 up to 1.2 V. Driving a 450 fF of capacitive load, the shifter's energy–delay product (EPD) is a 54% lower than a similar single supply level up shifter. Post–layout simulations, for every technological corner, temperature range from 25 up to 125 °C, operating input voltages and output capacitive loads (maximum of 740 fF), demonstrate the topology is fully functional without any impact on the static power consumption and the operating frequency of 500 MHz. Monte Carlo analysis shows the robustness of the proposed shifter within a 3σ device mismatch.

Calibrated 10 b 28 nm CMOS SAR ADC based on integer‐based split capacitors

A calibrated 10 b 5 MS/s 28 nm CMOS successive-approximation-register ADC based on an integer-based split capacitor array is presented. The proposed ADC employs a split capacitor array to optimise the overall power consumption, chip area and linearity performance. An attenuation capacitor between two capacitor arrays is implemented with an integer multiple of unit capacitors rather than a fraction of unit capacitors. The proposed calibration of capacitors reduces the non-linearity error caused by device mismatches in the conventional split capacitor array. The measured prototype ADC which has an active die area of 0.063 mm2 shows a maximum signal-to-noise-and-distortion ratio and spurious-free dynamic range of 59.25 and 70.44 dB, respectively, and consumes 42.5 μW at 0.7 V and 5 MS/s. Moreover, the measured differential non-linearity (NL) and integral NL are within 0.36 and 0.52 least significant bit, respectively, after calibration.

A 0.45–0.7 V 1–6 Gb/s 0.29–0.58 pJ/b Source-Synchronous Transceiver Using Near-Threshold Operation

A low-power source-synchronous multi-Gb/s transceiver is presented. Supply voltage is aggressively scaled to reduce power, and the speed penalty resulting from low-voltage operation is overcome by multiplexing transmitter/receiver synchronized by low-rate multi-phase clocks. Phase spacing errors incurred by device mismatches are corrected using a self-calibration scheme. The proposed phase calibration method uses a single digital DLL to calibrate all the phases, which makes it insensitive to offsets in the calibrating DLL. Fabricated in a 65-nm CMOS process, energy efficiency and data rate of the prototype transceiver vary from 0.29 to 0.58 pJ/bit and 1 to 6 Gb/s, respectively, as the supply voltage changes from 0.45 to 0.7 V.

SoC FPAA Hardware Implementation of a VMM+WTA Embedded Learning Classifier

This paper focuses on the circuit aspects required for an on-chip, on-line system on chip large-scale field-programmable analog array learning for vector-matrix multiplier (VMM) + winner-take-all (WTA) classifier structure. We start by describing the VMM+WTA classifier structure, and then show techniques required to handle device mismatch. The approach is initially explained using a VMM+WTA as a two-input XOR classifier structure. The approach requires considering the entire mixed-mode system, including the analog classifier data path, control circuitry for weight updates, and digital algorithm for computing digital weight updates and resulting floating-gate programming during the algorithm.

A CMOS quadrature VCO with optimized Colpitts topology for low-voltage applications

In this work, a new configuration of differential drain-to-source Colpitts LC voltage controlled oscillator (VCO) is proposed for low voltage applications. The circuit employs two capacitors in a cross-coupled positive feedback to separate the gate biasing of switching transistors from their drain dc voltages. This technique provides lower overdrive voltage for switching transistors which reduces the needing supply voltage. Besides, another positive feedback is imposed in this configuration which decreases the required transconductance for start-up oscillation. Also, a new quadrature VCO (QVCO) is presented by realizing two identical prior proposed Colpitts VCOs. The coupling technique used in the proposed QVCO improves the phase noise performance of the circuit. A linear analysis is presented to confirm that the oscillator can generate outputs with 90° phase difference. Additionally, the Monte Carlo (MC) simulation is performed to estimate the accuracy of the proposed circuit performance under various device mismatches.

An Analogue Neuromorphic Co-Processor That Utilizes Device Mismatch for Learning Applications

As the integrated circuit (IC) technology advances into smaller nanometre feature sizes, a fixed-error noise known as device mismatch is introduced owing to the dissimilarity between transistors, and this degrades the accuracy of analog circuits. In this paper, we present an analog co-processor that uses this fixed-pattern noise to its advantage to perform complex computation. This circuit is an extension of our previously published trainable analogue block (TAB) framework and uses multiple inputs that substantially increase functionality. We present measurement results of our two-input analogue co-processor built using a 130-nm process technology and show its learning capabilities for regression and classification tasks. We also show that the co-processor, comprised of 100 neurons, is a low-power system with a power dissipation of only $1.1~\mu \text{W}$ . The IC fabrication process contributes to randomness and variability in ICs, and we show that random device mismatch is favorable for the learning capability of our system as it causes variability among the neuronal tuning curves. The low-power capability of our framework makes it suitable for use in various battery-powered applications ranging from biomedical to military as a front-end analog co-processor.

Low power differential colpitts injection-locked frequency dividers using 0.18 μm CMOS technology

ABSTRACTIn this work, two new LC injection-locked frequency dividers (ILFDs) based on voltage-controlled oscillator are proposed. One of the proposed circuits is a divide-by-2 and the other is a divide-by-3 ILFD which are realized with a current-switching colpitts LC oscillator with one/two injection capacitors, respectively. A theoretical analysis is presented which confirms the operating principle of the proposed circuits. At the supply voltage of 1.5 V, the power consumption of the divide-by-2 and divide-by-3 ILFDs is 1.581 and 1.608 mW, respectively. At the incident power of 5 dBm, the locking range of divide-by-2 divider is from the incident frequency of 10.16 to 11.33 GHz and for divide-by-3 divider is 9.08 to 10.1 GHz. The proposed ILFDs were designed using a TSMC 0.18 μm RF CMOS technology. Additionally, the Monte Carlo simulation is performed to estimate the accuracy of the proposed circuit performances under various device mismatches.

Study and Designing of Fourth Order BEC Circuit for Flash Analog to Digital Converter using MUX based Encoder

Objectives: To design and study a fourth order Bubble error correction circuit for a Flash Analog to Digital Converter by making use of a Multiplexer based encoder. Methods/Statistical Analysis: A Thermometer to binary encoder acts as a vital element in the functioning of flash ADCs. Output of flash ADCs is in thermometer code. Ideally, Thermometer code shows single transition but in case of clock jitter and device mismatch, multiple transitions take place introducing bubbles in the code. This error leads to inaccurate encoding process. A Bubble error correction circuit has been proposed that eliminates bubble error upto fourth order as compared to existing circuit that eliminated error only upto third order. Simulation shows the transistor requirement of existing and proposed circuit is same thus making present circuit more efficient and acceptable. Findings: The Number of transistors required in different types of encoders can be understood through the tables. Although ROM based encoder along with BEC circuit requires 714 transistors which is less than other circuits. But since the conversion speed of ROM based encoder is relatively slow and because of constant static current which is used for presetting the encoder, the power consumption goes high and so ROM based encoder is avoided. Wallace tree requires lesser transistors but is unsuitable for the high speed of operations. Fat tree encoder along with BEC circuit requires 832 transistors. It has slightly less transistor requirement than proposed circuit but its difficult layout prevents us from using it. All the three encoder types mentioned in the table namely ROM based, Wallace tree and fat tree encoders are capable to remove bubble error only upto 3rd order. In case designing is done to remove higher order bubble error considers it to be fourth then definitely the transistor count will increase. However our proposed BEC circuit with MUX based encoder eliminates bubble error upto fourth order. It can be seen from the table ,the transistor count in new BEC circuit for removing fourth order error nearly matches the transistor count for removal of third order error by remaining encoders. Thus existing circuits and proposed circuit will have much difference in their efficiency of operation. Lesser number of transistor requirements makes our circuit more acceptable and efficient. Application/Improvements: Varying the (W/L) ratio may contribute in bringing changes in the delay and the average power dissipation making the circuit more efficient. CMOS inverter is susceptible to the process and the temperature variation. Temp variation would make the threshold voltage change so we may use another design whose comparator uses a self tuned inverter.

A Distance Detector with a Strip Magnetic MOSFET and Readout Circuit.

This paper presents a distance detector composed of two separated metal-oxide semiconductor field-effect transistors (MOSFETs), a differential polysilicon cross-shaped Hall plate (CSHP), and a readout circuit. The distance detector was fabricated using 0.18 μm 1P6M Complementary Metal-Oxide Semiconductor (CMOS) technology to sense the magnetic induction perpendicular to the chip surface. The differential polysilicon CSHP enabled the magnetic device to not only increase the magnetosensitivity but also eliminate the offset voltage generated because of device mismatch and Lorentz force. Two MOSFETs generated two drain currents with a quadratic function of the differential Hall voltages at CSHP. A readout circuit—composed of a current-to-voltage converter, a low-pass filter, and a difference amplifier—was designed to amplify the current difference between two drains of MOSFETs. Measurements revealed that the electrostatic discharge (ESD) could be eliminated from the distance sensor by grounding it to earth; however, the sensor could be desensitized by ESD in the absence of grounding. The magnetic influence can be ignored if the magnetic body (human) stays far from the magnetic sensor, and the measuring system is grounded to earth by using the ESD wrist strap (Strap E-GND). Both ‘no grounding’ and ‘grounding to power supply’ conditions were unsuitable for measuring the induced Hall voltage.

A 285-fsrmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a 285-fs rms integrated jitter at 3.328 GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is ‒242.4 dB.

Performance Analysis of Shared Buffer Router Architecture for Low Power Applications

An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a 285-fsSUBrms/SUB integrated jitter at 3.328 GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is ‒242.4 dB.

High performance single supply CMOS 0.45–1 V input to 1.1 V output level up shifter

This paper presents the design of a single supply CMOS level up shifter for low voltage and low energy consumption. The proposed voltage level converter is implemented using low threshold voltage transistors in 65nm CMOS technology. The shifter circuit designed for an output of 1.1V was verified, through the post–layout simulation, to be functional for an input voltage range of 0.45–1V. We compare our work with several other level shifters. With a 50fF of capacitive load, the shifter's energy–delay product is a 40% lower than a similar single supply level up shifter. Moreover, the measurements on the fabricated dies show that the proposed structure is able to drive a double capacitive load of up to 105fF, without any impact on the static power consumption. Monte–Carlo analysis demonstrates the robustness of the proposed shifter within a 3σ device mismatch.