Implementation of Low Supply Rail-to-Rail Differential Voltage Comparator on Flexible Hardware for a Flash ADC

Abstract

A 4-bit flash ADC utilizing the advantage of digital-based differential voltage comparator is presented in this paper. This circuit has an advantage of digital circuit concept and can be easily migrated to lower technologies. Also, the digital circuits are less sensitive to the noise and device mismatches can be synthesized and auto place and route (P&R) using EDA tools. The design of the proposed comparator is based on the standard cells implementation. As the proof of concept this comparator is implemented on Xilinx Basys-3 Artix-7 FPGA kit. The prototype of complete 4-bit Flash ADC is designed in 180[Formula: see text]nm CMOS technology with 1.8[Formula: see text]V supply voltage. The measured values of ENOB, SNDR, SNR and SFDR are 3.6, 23.43[Formula: see text]dB, 25.2[Formula: see text]dB and 30.1[Formula: see text]dB, respectively at 33.20[Formula: see text]MHz input frequency and 200[Formula: see text]MHz clock frequency. The total power consumed by the 4-bit flash ADC is 2.14[Formula: see text]mW. The calculated value of DNL and INL is [Formula: see text] LSB and [Formula: see text] LSB respectively.