Device Failure Mechanisms Research Articles

Structural Integrity and Crystal Defect Generation in VLSI/ULSI Devices

The microstructure‐related problems during process development for very(ultra)‐large‐scale integration (VLSI/ULSI) circuits are studied by transmission electron microscopy (TEM). An improved method of preparing a TEM cross section is described. Typical micrographs are presented to illustrate various process‐induced microstructures. The relationships of these microstructures to the processes and their effects on the device quality are discussed. These studies demonstrate that TEM analysis can be used for the identification of device failure mechanisms and the establishment of process‐microstructure relationships in submicron devices.

Correlation between thermal resistance, channel temperature, infrared thermal maps and failure mechanisms in low power MESFET devices

Abstract Channel temperature T ch of GaAs MESFETs, determined by means of electrical measurements ( ΔV gs ), has been compared and correlated with thermal maps obtained by high resolution infrared microscopy. Results show that in low power devices with a small number of gates, the value of T ch derived from ΔV gs measurements is close to the maximum values of temperature measured on the hottest junctions on the chip. Local thermal inhomogeneities, in particular those observed in devices characterized by high values of R th , can explain and confirm results of failure analyses of MESFETs submitted to accelerated life tests in operating conditions where degradation phenomena occur in localized areas of the device.

Failure mechanisms of TiN thin film diffusion barriers

Reactively sputtered TiN has been studied for use as a diffusion barrier in the Al/TiN/Ti/Si metallization scheme in silicon-on-sapphire (SOS) integrated circuits. The diffusion barrier properties of TiN were found to depend critically on the deposition parameters, which result in different microstructure and oxygen concentration in the film. Two types of TiN thin films were studied in these experiments. Under no-bias conditions, dark brown colored films (called B films) with low density (3.22 g cm −3 ), high electrical resistivity (about 400 μΩ cm) and 5–8% O 2 were obtained. At - 75 V d.c. substrate bias, bright golden colored films (called G films) with high density (about 5.0 g cm −3 ), low resistivity (about 20 μΩ cm) and negligible O 2 were obtained. The G films were found to stop the silicon diffusion. But there was formation of intermetallics at the Al/TiN interface, which resulted in decomposition of the TiN film. On the other hand, the B films, though they were permeable to silicon, were found to stop this interaction. Based on the above results, a new metallization (Al/TiN(B)/TiN(G)/Si) was examined. RBS did not indicate any interactions after 2 h of annealing at 600 °C. The film microstructure was studied by cross-sectional and planar TEM samples. Also, these films were studied by RBS, AES, XRD and XPS to understand the diffusion and device failure mechanisms.

Failure mechanisms in semiconductor devices, E. A. Amerasekera and D. S. Campbell. Wiley, Chichester, 1987. Number of pages: 205. Price: $19.95

Failure mechanisms in semiconductor devices, E. A. Amerasekera and D. S. Campbell. Wiley, Chichester, 1987. Number of pages: 205. Price: $19.95

Reliability evaluation of plastic packaged devices for long life applications by THB test

The reliability of transistors, bipolar and CMOS integrated circuits encapsulated in different types of plastic packages was investigated by using the 85°C/85% R.H. test with applied bias and the results compared with a long term operating life test. Particular attention was devoted to pointing out the influence of technology, process control and working conditions on device reliability and failure mechanisms. In micropackaged transistors the importance of surface passivation in protecting the devices against gold corrosion was forcused, while the need of good process control was confirmed by the results of the test on micropackaged linear integrated circuits. In dual-in-line CMOS integrated circuits silicon nitride and polymide give, in general, a superior protection, but good results were obtained also with normal P-glass passivation when a clever arrangement of layout design rules was adopted. Results obtained exhibit a significant improvement in the reliability of plastic packaged devices, with the best figures showing no failures after 15,000 hours at 85°C/85% R.H. test with bias.

Failure Mechanisms in Semiconductor Devices, E. A. AMERASEKERA, (to be published by Gordon & Breach Science Publishers)

Failure Mechanisms in Semiconductor Devices, E. A. AMERASEKERA, (to be published by Gordon & Breach Science Publishers)

Characterization of bias sputtered metallization for IC technology

Abstract The development of custom integrated circuits with better performance and higher packing densities has led to the need for multi-level interconnection technology. Such circuits require plasma etching for dimensional control of the interconnecting vias and improved metal deposition techniques for coverage of the etched features. Substrate bias is shown to improve the coverage of magnetron sputtered aluminium alloy over abrupt plasma etched steps but is very sensitive to the step profile. Increases in the metal resistance and the formation of cracks at the base of the steps place limitations on the useful range of bias voltage. Analytical techniques have been used to characterize compositional changes of the bias sputtered films and assess their influence on established device failure mechanisms.

How parts fail: A fundamental explanation for any part failure exists, and it's up to the failure analyst to find the cause with modern sleuthing

Gives an understanding of how semiconductor and other electronic parts fail is essential to improving the reliability of devices as well as that of the systems in which they are used. Such failure analyses help identify device failure modes, mechanisms, and stress factors that influence degradation. A device can fail in a catastrophic, degradation, or intermittent mode. Electrical failures are usually opens, shorts, or parameters out of specification. The failure mechanism is the basic chemical or physical change that results in an identifiable failure mode. Parts failures can be labeled as early fallout , stress-related, and wearout. Early failures are often linked to design and manufacturing flaws or to reliability screen test escapes but can be stress-related. Normal operating stresses cause most failures that occur after the early ones. Wearout failures are linked to aging and deterioration.

A survey of corrosion failure mechanisms in microelectronic devices: G. L. Schnable, R. B. Comizzoli, W. Kern and L. K. White RCA Review, 40, 416 (December 1979)

A survey of corrosion failure mechanisms in microelectronic devices: G. L. Schnable, R. B. Comizzoli, W. Kern and L. K. White RCA Review, 40, 416 (December 1979)

Investigation of the molecular processes controlling corrosion failure mechanisms in plastic encapsulated semiconductor devices

Abstract Corrosion related failures of plastic encapsulated semiconductor devices have been observed during accelerated aging tests, with some indication of increased failure rates in flame-retarded molding compounds. Dynamic pyrolytic-mass spectrometry, thermogravimetric analysis and differential scanning calorimetry, combined with aqueous extraction and X-ray fluorescence analyses, are used to study the detailed chemistry involved in the decomposition of novolac-epoxy resins during thermal aging. The data obtained reveal that extensive outgassing occurs from several sources in different temperature ranges. In particular, methyl chloride, released from residual chlorine-containing species used in the polymerization process, is identified as a dominant product at device testing temperatures (200°C). Inclusion of a brom-inated flame retardant in the epoxy formulation, however, results in only minor differences in the volatile product composition at temperatures ≤200°C. The major release of bromine products is observed at higher temperatures (> 300°C). A detailed discussion of the molecular processes governing polymer outgassing in the different temperature ranges is presented. Special emphasis is placed on the comparison of a flame retarded and non-flame retarded novolacepoxy formulation. Finally, the implications of the results to macroscopic corrosion failure mechanisms in semiconductor devices are discussed.

A survey of corrosion failure mechanisms in microelectronic devices : George L. Schnable, Robert B. Comizzoli, Werner Kern and Lawrence K. White. RCA Review, 40, 416 (December 1979)

A survey of corrosion failure mechanisms in microelectronic devices : George L. Schnable, Robert B. Comizzoli, Werner Kern and Lawrence K. White. RCA Review, 40, 416 (December 1979)

Screening methods and experience with MOS memory

Abstract This paper describes the experience of Bell-Northern Research and Northern Telecom Ltd. with MOS dynamic RAMS in high reliability switching systems. Various failure mechanisms of the MOS memory devices and the screening procedures, implemented in Northern Telecom Ltd. to weed out weak devices, are explained. The resultant device drop-out rates in manufacturing and the effect of this comprehensive pre-conditioning on the field failure rate of MOS memory cards are discussed.

Field Oxide Inversion Effects in Irradiated CMOS Devices*

The primary failure mechanism of CMOS devices in an ionizing radiation environment is a threshold voltage shift in both the p-channel and the n-channel devices due to a buildup of radiation-induced fixed charge in the silicon dioxide and the creation of surface states at the silicon-silicon dioxide interface. It has been observed that many CMOS device types exhibit milliampere range post-rad n-channel leakage for doses between 104 - 105 rad (Si) even though the gate oxide threshold shift is much less than that required for inversion in the channel region. This is caused by field oxide inversion under the gate metal due to improper or a lack of guardbanding of the n-channel device for a radiation environment. The solution to this problem in hardening CMOS devices involves guardbanding the n-channel devices and extending the gate oxide under the gate metallization over the guardband. Experimental results on devices which utilize this technique has shown it to be an effective solution to the problem. Data on several types of CMOS devices are presented to illustrate the n-channel leakage problem and the solution. Special guardbanding problems encountered with silicon gate on bulk Silicon devices are also described and possible solutions to these problems are discussed.

Stress testing FET gates without the use of test patterns

A test technique is described for stressing each FET gate in multiphase dynamic random logic FET circuits incorporated in a large-scale integrated (LSI) device. This 100 percent gate stressing essentially results from sequencing the clock signals in reverse order to that sequence required to transfer information through the logic paths to perform the circuit logic functions. When the clock signals are run in this reverse order, no input test patterns are required. Stressing by this method helps guarantee the reliability of shipped devices by preventing the shipment of possible bad lots or devices which are likely to fail in the field due to device failure mechanisms such as sodium ion migration and/or gate breakdown.

Photoinjection Studies of Charge Distributions in Oxides of MOS Structures

Determination of the nature and distribution of oxide charge in MOS structures is important to an understanding of oxide charging phenomena. In addition to their relevance to device failure mechanisms, it appears that charging phenomena may be used to advantage in memory device applications. The physical mechanism dominating the voltage dependence of photoinjected currents in SiO2 is the scattering of electrons in the region of the oxide between the injecting electrode and the image force potential maximum. Since the spatial position of the potential maximum depends on the electric field resulting from space charge in the oxide as well as the field due to the applied voltage, analysis of the V-I characteristics of photoinjected currents can provide information about the spatial location of oxide charge. Presented in this paper are the results of an analysis of the effects of oxide space charge on the voltage dependence of photoinjected currents. It is shown that effective charge distributions in SiO2 can be nondestructively profiled over a range from about ten to several hundred angstroms from the injecting electrode. Since photoinjection V-I characteristics depend on electric field at the potential maximum in the oxide, whereas C-V characteristics depend on the field just inside the semiconductor, analysis of both characteristics permits distinction between charge in the oxide a distance greater than about 10 Å and charge located at the interface. The results of experiments on Au–SiO2–Si structures in which charge has been purposely introduced into the oxide are presented, and it is shown that the interface fixed charge and the charge associated with fast surface states extend no further than about 20 Å into the oxide from the Si–SiO2 interface.