Field Oxide Inversion Effects in Irradiated CMOS Devices*

Abstract

The primary failure mechanism of CMOS devices in an ionizing radiation environment is a threshold voltage shift in both the p-channel and the n-channel devices due to a buildup of radiation-induced fixed charge in the silicon dioxide and the creation of surface states at the silicon-silicon dioxide interface. It has been observed that many CMOS device types exhibit milliampere range post-rad n-channel leakage for doses between 104 - 105 rad (Si) even though the gate oxide threshold shift is much less than that required for inversion in the channel region. This is caused by field oxide inversion under the gate metal due to improper or a lack of guardbanding of the n-channel device for a radiation environment. The solution to this problem in hardening CMOS devices involves guardbanding the n-channel devices and extending the gate oxide under the gate metallization over the guardband. Experimental results on devices which utilize this technique has shown it to be an effective solution to the problem. Data on several types of CMOS devices are presented to illustrate the n-channel leakage problem and the solution. Special guardbanding problems encountered with silicon gate on bulk Silicon devices are also described and possible solutions to these problems are discussed.