Device Design Tradeoffs Research Articles

(Invited) Oxide Semiconductor Gain Cell Memory

The energy and delay consumed by the off-chip memory (DRAM) and memory-to-logic chip data movement becomes the bottleneck (known as the memory wall) for the computing systems nowadays, especially for abundant-data computing and neural network accelerators. Larger on-chip memory capacity with high bandwidth can be a solution, yet it is difficult to achieve using SRAM and DRAM. Oxide semiconductor FET (OSFET)-based gain cell memory on the logic platform provides higher density than SRAM due to 3D stacking and is an attractive complement to off-chip DRAM. OSFET with extremely low leakage is used as the write transistor for long retention time, while the read transistor can either adopt OSFET for multiple-layer stacking (OS-OS gain cell) or Si FET for higher read speed (Hybrid gain cell). Designing OSFET gain cell is more than simply choosing materials/device designs that have the lowest off-state leakage current for the longest retention time. Atomic Layer Deposition (ALD) Indium Tin Oxide (ITO) FET is chosen to balance retention time with memory bandwidth. With material, process, and device co-design, the ITO films deposited by ALD with TMIn precursor, 9:1 In:Sn cycle ratio, and 2nm thickness exhibited optimized characteristics for OSFET-based gain cell. The experimentally optimized device exhibits low off-current 2×10-18 A/µm, high on-current 26.8 µA/µm, low SS 70 mV/dec, and high mobility 27 cm2/Vs. It also shows good stability with small VTH shift < 0.2 V under 125 °C, low PBS shift < 0.35 V and low NBS shift < 0.1 V under 1000s bias stress. Oxide semiconductor transistors is an accumulation mode transistor that requires a gate electric field to turn off the transistor. The transistor design calls for nanometer-thin oxide semiconductor channels. Significant device design tradeoffs exists between high on-current, low off-current, short gate length scalability, and the setting of proper threshold voltages. This talk will give an overview of the above experimental achievements today and the device design considerations for future gain cell memories.

(Keynote) High-Performance Carbon Nanotube Transistors for Logic Platform

Low-dimensional 1D and 2D materials hold promise as candidate channel materials for highly scaled and high-performance transistors beyond the limits of silicon-based transistors. This talk will first motivate transistors built on low-dimensional channels due to the significant speed, energy efficiency, and transistor density benefits enabled by their electronic and physical properties. This talk will focus on 1D carbon nanotube (CNT) semiconductors and describe the advanced device component process modules that have been demonstrated, explaining both the fundamental mechanisms of operation and device-level performance objectives. Single-CNT FET experimental studies give insight into the quality of (1) low resistance N- and P- contacts down to 10 nm contact length, (2) high-capacitance gate dielectrics optimized for deposition on SP2 carbon surfaces, and (3) controlled N- and P- remote dielectric doping. To achieve high current density each transistor must contain multiple CNTs, therefore we will review state-of-the-art strategies to assemble densely aligned arrays of CNT with controlled CNT spacing between 2-10 nm and uniform electronic bandgap. The final portion of the talk will highlight recent advances from our team and others to integrate the best device components together to demonstrate high-performance carbon nanotube MOSFETs. We will elaborate on the remaining challenges and provide a summary of device design tradeoffs that will help guide future studies.We are grateful for support and collaboration from TSMC Corporate Research, DoD, Stanford SystemX Alliance, Stanford Nanofabrication Facility, Stanford Nano Shared Facility, and the University of California at San Diego.

Turn-on of High-Voltage SiC Thyristors for Fast-Switching Applications

This paper is focused on the characterization of the turn-ON transition of high-voltage SiC thyristors of different epi-layer thicknesses and active-area sizes to determine their suitability and limitations in high- $dI/dt$ , fast-switching applications. The unique aspects of this paper include the very high current density being switched through the thyristors over a short period of time at initial turn-ON, resulting in very high instantaneous dissipated power over the small device volume. The devices that were characterized were 6-kV, 0.5-cm2 thyristors; 10-kV, 1.05-cm2 thyristors; and 15-kV, 1.05-cm2 thyristors, all fabricated by Cree, Inc. (now Wolfspeed) for the U.S. Army Research Laboratory. The highest dI/dt and the current density were 13 kA/ms and 3.2 kA/cm2 for a parallel pair of 0.5-cm2 thyristors, with pulsed current peaking 250 ns from initial gate trigger. All devices evaluated were capable of switching a current pulse >2 kA/cm2 within a period of less than $2~\mu \text{s}$ . These evaluations have broad application in helping to inform SiC device design tradeoffs for increasing epi thickness, increasing device area, and the effects of lifetime enhancement processes. Results are also presented for initial exploration of fast-switching applications for these devices.

Impact of Channel and Metal Gate Work Function on GS-DG MOSFET: A Linearity Analysis

The current work reveals the substantial benefits of the various gate and channel engineering concepts, as well as the combination of both on the gate stack double gate (GS-DG) MOSFET. It is demonstrated that post implementation of tri material (TM) gate electrode and halo doping in the channel are significantly alleviated various performance metrics of GS-DG MOSFET. The study is based on surface potential, e-mobility, e-field, threshold voltage (Vth), subthreshold swing (SS), on-current (Ion), off-state current (Ioff), transconductance (gm1), second order voltage intercept point (VIP2), third order voltage intercept point (VIP3), third order intercept input power (IIP3), intermodulation distortion (IMD3), 1-db compression point, and higher order transconductance coefficients gm2, and gm3. Optimal device design parameters and trade-offs are examined through 2-D Sentaurus device simulator. The results are significant and reliable for RFICs with nanoscale MOSFETs.

High-Current-Gain InP/GaInP/GaAsSb/InP DHBTs With $f_{T} = \hbox{436}\ \hbox{GHz}$

Combining a pseudomorphically strained (Ga,In)P emitter with a GaAs0.6Sb0.4 base effectively eliminates the emitter heterojunction type-II conduction band offset in InP/GaAsSb double heterojunction bipolar transistors (DHBTs). A peak fT of 436 GHz at JC = 10 mA/mum2, with BVCEO = 3.8 V, is achieved with 0.6 times 5 mum2 InP/GalnP/GaAsSb DHBTs with a 75-nm InP collector. Compared to a binary InP emitter, the (Ga,In)P emitter doubles the DC current gain from 166 to 338 for otherwise identical devices. These are the highest DC current gain and cutoff frequencies to date in uniform base GaAsSb DHBTs. The gain improvement reported here will greatly facilitate device design tradeoffs that are encountered while scaling InP/GaAsSb DHBTs toward higher frequencies by allowing higher base doping levels and smaller emitter geometries.

Gain-switched GaAs vertical-cavity surface-emitting lasers

The authors have gain-switched GaAs vertical-cavity surface-emitting lasers (VCSELs) using sinusiodal electrical modulation at rates between 1.5 and 8 GHz and devices with operating wavelengths between 820 and 860 nm. The shortest pulse obtained directly from such lasers was 24 ps. The time-bandwidth products were between 0.6 and 3, which is smaller than those observed for gain-switched, single-frequency, edge-emitting lasers. Some of the excess bandwidth is caused by linear chirp, which was compensated using linear dispersion in single-mode optical fiber. The shortest compressed pulse was 15 ps. The pulses contained significant nonlinear chirp, however, which reduced the expected compression factor for linear dispersion to a factor of 2. The timing jitter for gain-switched pulse trains was 4-6 ps, which is comparable to that observed for the edge-emitting lasers. Device design tradeoffs which affect the duration of the pulses from gain-switched VCSELs are discussed. >

Computer-aided performance assessment of fully depleted SOI CMOS VLSI circuits

A physical model for the fully depleted submicrometer SOI MOSFET is described and used to assess the performance of SOI CMOS VLSI digital circuits. The computer-aided analysis is focused on both problematic and beneficial effects of the parasitic bipolar junction transistor (BJT) in the floating-body device. The study shows that the bipolar problems overwhelm the benefits, and hence must be alleviated by controlling the activation of the BJT via device design tradeoffs. A feasible approach to the needed design optimization is demonstrated by veritable device/circuit simulations, which also predict significant speed superiority of SOI over bulk-silicon CMOS circuits in scaled, submicrometer technologies. >

A fully integrated silicon-based 40-V thermal ink jet IC

A fully-integrated silicon-based thermal ink jet printhead which produces high speed, laser-quality printing at 300 spots per inch resolution is described. Monolithic integration of the 5-V logic circuitry, 13-V predriver circuitry, 40-V MOSFETs, and 192 n + polysilicon heater elements requires multiple process and device design trade-offs. The TIJ printhead is customer replaceable and must be protected from far greater static discharges than normal VLSI circuits. Design issues and failure mechanisms of the power MOSFETs and ESD protection devices are discussed. Two-dimensional simulations which include parasitic bipolar action and lattice heating illustrate the design concepts. Electrical characteristics of the 40-V power MOSFETs and 16-kV ESD protection devices are presented.

Power n-MOSFET design for a 40-V 192-element thermal ink jet IC

A silicon-based thermal ink jet (TIJ) printhead which produces high-speed, laser-quality printing with a 300 spot per inch resolution has been designed, fabricated, and tested. The 5-V addressing logic, 13-V predriver circuitry, 40-V power MOSFET switches, and 192-drop ejectors are integrated on a single chip, and controlled by only seven external connections. The authors discuss the specific TIJ process and device design tradeoffs, especially focusing on the 40-V smart-power MOSFETs, and illustrate them with 2-D numerical modeling and experimental device data.

Process limitation and device design tradeoffs of self-aligned TiSi/sub 2/ junction formation in submicrometer CMOS devices

Submicrometer CMOS transistors require shallow junctions to minimize punchthrough and short-channel effects. Salicide technology is a very attractive metallization scheme to solve many CMOS scaling problems. However, to achieve a shallow junction with a salicide structure requires careful optimization for device design tradeoffs. Several proposed techniques to form shallow titanium silicide junctions are critically examined. Boron, BF/sub 2/, arsenic, and phosphorus dopants were used to study the process parameters for low-leakage TiSi/sub 2/ p/sup +//n and n/sup +//p junctions in submicrometer CMOS applications. It is concluded that the dopant drive-out (DDO) from the TiSi/sub 2/ layer to form a shallow junction scheme is not an efficient method for titanium salicide structure; poor device performance and unacceptably leaky junctions are obtained by this scheme. The conventional post junction salicide (PJS) scheme can produce shallow n/sup +//p and p/sup +//n junctions with junction depths of 0.12 to 0.20 mu m below the TiSi/sub 2/. Deep submicrometer CMOS devices with channel length of 0.40 to 0.45 mu m can be fabricated with such junctions. >

Superconductive convolver

Concepts for realizing superconductive convolvers capable of processing analog signals having bandwidths up to 10 GHz have been developed and are being implemented. A preliminary convolver structure with 19 taps and a 14-ns interaction length has recently been demonstrated. This device employs a superconductive transmission line as a low-loss delay element and superconductive tunnel junctions as nonlinear mixing elements. The niobium delay line provides the relative shifting of signal and reference waveforms, niobium/niobium-oxide/lead mixers with proximity taps provide local multiplication of the two waveforms, and a short output transmission line provides coherent summation of the local products. The principles of device operation, design tradeoffs and experimental results will be presented. Convolvers can provide the essential programmable matched-filter component for extremely wide-bandwidth spread-spectrum communication systems. It appears feasible to produce a convolver with an interaction time of about 100 ns and signal processing gains of up to 1000. This superconductive analog device offers the potential of providing a real-time programmable signal processing function with the digital equivalent of about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> operations/sec.