Detrapping Characteristics Research Articles

A Simple Method to Extract the Thermal Resistance of GaN HEMTs From De-Trapping Characteristics

This paper proposes a new method for extracting the thermal resistance of GaN-based HEMTs using pulse recovery data. After the device temperature and trapping state are established from different quiescent power dissipations for several base-plate temperatures, the recovery profile of the drain current is measured. The recovery time is then used as a temperature-sensitive electrical parameter to extract the thermal resistance of the device. The proposed method has been applied to a Schottky-gate HEMT on SiC, for which a thermal resistance of 15.7 °C-mm/W was extracted, a value in good agreement with others reported for similar devices. Comparison with the one obtained from a step response is also done. Finally, the uncertainties of the proposed method related to the pulse width, temperature, percentage of the drain current recovery time, and averaging procedure are discussed.

Near-Infrared Artificial Optical Synapse Based on the P(VDF-TrFE)-Coated InAs Nanowire Field-Effect Transistor.

Optical synapse is the basic component for optical neuromorphic computing and is attracting great attention, mainly due to its great potential in many fields, such as image recognition, artificial intelligence and artificial visual perception systems. However, optical synapse with infrared (IR) response has rarely been reported. InAs nanowires (NWs) have a direct narrow bandgap and a large surface to volume ratio, making them a promising material for IR detection. Here, we demonstrate a near-infrared (NIR) (750 to 1550 nm) optical synapse for the first time based on a poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE))-coated InAs NW field-effect transistor (FET). The responsivity of the P(VDF-TrFE)-coated InAs NW FET reaches 839.3 A/W under 750 nm laser illumination, demonstrating the advantage of P(VDF-TrFE) coverage. The P(VDF-TrFE)-coated InAs NW device exhibits optical synaptic behaviors in response to NIR light pulses, including excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF) and a transformation from short-term plasticity (STP) to long-term plasticity (LTP). The working mechanism is attributed to the polarization effect in the ferroelectric P(VDF-TrFE) layer, which dominates the trapping and de-trapping characteristics of photogenerated holes. These findings have significant implications for the development of artificial neural networks.

DC Breakdown of XLPE Modulated by Space Charge and Temperature Dependent Carrier Mobility

In this paper, the dependence of XLPE electrical breakdown on carrier mobility controlled by both electric field and temperature is evaluated by simulations and experiments. The molecular chain displacement model incorporating the thermoelectric effect of carrier mobility is examined to elucidate the experimental results. Trapping and de-trapping characteristics of space charge and mobility dynamics are modeled using hopping and Poole-Frenkel mechanisms. The experimental outcomes reveal that the DC electrical breakdown reduces with corresponding increment in temperature and thickness. Trapping parameters are estimated from experiments for simulations. The DC breakdown strength from experiments represents an inverse power relation with both the insulation thickness and temperature. The simulation results of molecular chain model with hopping mobility express more permanence with experimental results in comparison with Poole-Frenkel mobility.

Investigations on charge trapping and de-trapping properties of polymeric insulators through discharge current measurements

It is generally accepted that formation and accumulation of space charge in polymeric insulation is a critical issue in the design of high voltage electric systems, as it leads to insulation degradation and premature failure under high voltage surges and polarity reversals. Even at service stress level, accumulation of space charge may cause electrothermal aging. The insulation degradation and aging is reflected in the trapping and detrapping characteristics of the insulation, making it a useful aging marker. Space charge measurement methods are frequently used for trapping and de-trapping analysis. However, estimation of charge trapping and de-trapping behavior is very difficult due to the involvement of material properties and also partly due to the fact that proper measurement of space charge is itself a very complicated issue, requiring very sophisticated experimental arrangement and signal processing techniques. Moreover, application of these methods is limited to polymeric insulations of certain geometries (planar or radial). In this paper, the charge trapping and de-trapping behavior of low density polyethylene (LDPE), a widely used polymeric material for electrical insulation purpose, have been investigated employing a direct method based on the discharge characteristics obtained after the sample was stressed for short durations. A relationship is established between the de-trapped charge and the extracted charge measured from the discharge current. From this relationship a relative distribution of trapped charges across different trap depths was obtained. It was noticed that the trapped charge distribution is of exponential nature in the trap depth range of 0.93–1.11 eV. The presented method facilitates direct estimation of trap distribution independent of the insulation geometry. It was also observed that the trapped charge is highly dependent on the applied field.

Balancing Surface Hydrophobicity and Polarizability of Fluorinated Dielectrics for Organic Field‐Effect Transistors with Excellent Gate‐Bias Stability and Mobility

It is demonstrated that treating dielectrics with fluorinated polymers, which have excellent hydrophobicity, chemical inertness, and the lowest polarizability, yields a semiconductor‐compatible surface energy and excellent charge detrapping characteristics. Fluorocopolymers, polystyrene‐random‐poly(2,3,4,5,6‐pentafluorostyrene) (PS‐r‐PPFS) copolymers with different 2,3,4,5,6‐pentafluorostyrene (PFS) loadings, are synthesized to modify a SiO2 gate dielectric using radical polymerization. Surface energy (γ) of the copolymer‐treated SiO2 dielectrics decreases from 40.7 to 24.0 mJ m−2 with increasing PFS mol% in the copolymer. Pentacene organic field‐effect transistors (OFETs) show field‐effect mobility (μFET) values ranging from 0.82 (for 0 mol% PFS) to 0.25 cm2 V−1 s−1 (for 100 mol% PFS). Enhancing the bias stress stability without affecting the μFET value is achieved via the introduction of a small mol% fluorocarbon segments onto the PS‐r‐PPFS backbone. 15 mol% PFS‐loaded fluorocopolymer‐coated SiO2 substrate yields a γ value of 35 mJ m−2, close to that (38 mJ m−2) of the lowest‐γ crystal surface of pentacene, and the corresponding OFETs have μFET values up to 0.81 cm2 V−1 s−1 and excellent gate‐bias stress stability in comparison to the rich fluorinated dielectric systems, which has degraded μFET values ranging from 0.2 to 0.4 cm2 V−1 s−1.

Memory Characteristics of SiSb NCs Embedded in MOS Capacitor Structure

Metal-oxide-semiconductor capacitors embedded with the Si16Sb84 nanocrystals have been fabricated and studied for their charge trapping, detrapping, and retention characteristics. Si16Sb84 NCs were achieved by annealing at 250°C.Both holes and electrons can be trapped to the nanocrystal-embedded dielectric stack depending on the polarity of the applied gate voltage. Charges trapped to the NCs, which are not observed in the control sample. More than half of the originally trapped charges can be retained in the embedded NCs for more than 10 yr. The nanocrystalline Si16Sb84 embedded in MOS capacitors is useful for this nonvolatile memory device.

Organic nonvolatile memory devices utilizing intrinsic charge-trapping phenomena in an n-type polymer semiconductor

Charge trapping is an undesirable phenomenon and a common challenge in the operation of n-channel organic field-effect transistors. Herein, we exploit charge trapping in an n-type semiconducting poly (naphthalene diimide-alt-biselenophene) (PNDIBS) as the key operational mechanism to develop high performance, nonvolatile, electronic memory devices. The PNDIBS-based field-effect transistor memory devices were programmed at 60 V and they showed excellent charge-trapping and de-trapping characteristics, which could be cycled more than 200 times with a current ratio of 103 between the two binary states. Programmed data could be retained for 103 s with a memory window of 28 V. This is a record performance for n-channel organic transistor with inherent charge-trapping capability without using external charge trapping agents. However, the memory device performance was greatly reduced, as expected, when the n-type polymer semiconductor was end-capped with phenyl groups to reduce the trap density. These results show that the trap density of n-type semiconducting polymers could be engineered to control the inherent charge-trapping capability and device performance for developing high-performance low-cost memory devices.

Memory functions of nanocrystalline cadmium selenide embedded ZrHfO high-k dielectric stack

Metal-oxide-semiconductor capacitors made of the nanocrystalline cadmium selenide nc-CdSe embedded Zr-doped HfO2 high-k stack on the p-type silicon wafer have been fabricated and studied for their charge trapping, detrapping, and retention characteristics. Both holes and electrons can be trapped to the nanocrystal-embedded dielectric stack depending on the polarity of the applied gate voltage. With the same magnitude of applied gate voltage, the sample can trap more holes than electrons. A small amount of holes are loosely trapped at the nc-CdSe/high-k interface and the remaining holes are strongly trapped to the bulk nanocrystalline CdSe site. Charges trapped to the nanocrystals caused the Coulomb blockade effect in the leakage current vs. voltage curve, which is not observed in the control sample. The addition of the nanocrystals to the dielectric film changed the defect density and the physical thickness, which are reflected on the leakage current and the breakdown voltage. More than half of the originally trapped holes can be retained in the embedded nanocrystals for more than 10 yr. The nanocrystalline CdSe embedded high-k stack is a useful gate dielectric for this nonvolatile memory device.

Charge Trapping and Detrapping in nc-RuO Embedded ZrHfO High-k Thin Film for Nonvolatile Memory Applications

The charge trapping and detrapping characteristics of the nc-RuO embedded Zr-doped HfO2 (ZrHfO) high-k MOS capacitor have been studied. The memory function of the capacitor is mainly contributed by hole trapping during the forward sweep from −9 V to +9 V and electron trapping during the backward sweep from +9 V to −9 V. The time- and bias-dependent stress test results show that the hole-trapping efficiency is higher than the electron-trapping efficiency due to different charge trapping sites and supply mechanisms. In order to delineate the detailed mechanisms, samples were characterized with the frequency-dependent conductance-voltage curves, relaxation currents, ramp-relax current measurements, and retention characteristics. Although most electrons are deeply trapped in the bulk nc-RuO sites, a portion of holes are loosely trapped at the nc-RuO/ZrHfO interface due to the lost of the short-term retention capability. The deeply-trapped holes and electrons were strongly held for a long period.

P‐28: The Effect of AC Bias Frequency on Threshold Voltage Shift of the Amorphous Oxide TFTs

AbstractWe investigated AC bias stress instability of indium‐gallium‐zinc‐oxide (IGZO) Thin‐film transistors (TFTs). AC bias frequency dependence showed different aspect in IGZO TFTs and a‐Si:H TFTs. Influencing factors to AC bias frequency dependence of instability is charge accumulation characteristic under negative bias stress, and detrapping characteristics of shallow trapped charges under positive bias stress.

Constant voltage stress induced charge trapping and detrapping characteristics of the Si3N4 uniaxial strained n-channel metal-oxide-semiconductor field-effect-transistor with fluorinated HfO2/SiON gate stack

Charge trapping and detrapping characteristics of Si3N4 contact etch stop layer (SiN CESL) uniaxial strained n-channel metal-oxide-semiconductor field-effect-transistor (nMOSFET) with fluorinated HfO2/SiON gate stack have been investigated for the first time. Smaller threshold voltage shift can consequently obtain for the SiN CESL strained nMOSFET with fluorinated HfO2/SiON gate stack, primarily due to passivation of oxygen vacancies and dangling bonds by either nitrogen or fluorine atoms. However, the SiN CESL strained nMOSFET with fluorinated gate stack inevitably exhibits less charge detrapping ratio, which means greater part of stress-induced charges would remain in the gate stack after nitrogen or fluorine incorporation, respectively.

Charge Trapping and Detrapping Behavior of Fluorinated $\hbox{HfO}_{2}/\hbox{SiON}$ Gate Stacked nMOSFET

The charge trapping and detrapping characteristics of the fluorinated hafnium oxide/oxynitride (HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /SiON) gate stack are investigated. Although incorporation of fluorine in the bulk stack had been proven to eliminate both bulk and interface trap densities due to Hf-F and Si-F bond formation, respectively, the effective trapping barrier of the device with fluorine incorporation (1.29 eV) is deeper than without fluorine incorporation (1.13 eV), indicating that the detrapping ability of the fluorinated devices may limit future fluorine process applications.

Observing two stage recovery of gate oxide damage created under negative bias temperature stress

We study the hysteresis in threshold voltage shift during alternating gate bias ramps (drain current vs gate voltage (IdVg) sweeps) after negative bias temperature stress and compare the results with carefully recorded charge pumping measurements. This allows us to clearly identify three different types of defects. All defect types have in common that their charge state depends on the position of the Fermi level and that they introduce a broad density of states (DOS) in the vicinity or within of the silicon band gap. Defect I is fully recoverable, defect II is similar to defect I in terms of DOS but does not recover, while defect III can be attributed to the conventional interface states. With a precise microstructural model in mind, and by using specific test chips, which allow us to vary stress bias and temperature quasiarbitrarily, we come to the conclusion that the carrier trapping and detrapping characteristics of stress induced defects can be controlled by temperature and electric field in a similar way, but that irrevocable structural relaxation is mainly influenced by temperature. Based on these ideas, we present a measurement method which can be used to energetically profile the relaxation of stress induced oxide defects.

Charge trapping and detrapping characteristics in amorphous InGaZnO TFTs under static and dynamic stresses

We have investigated the static and dynamic bias stress-induced charge trapping and detrapping phenomenon in amorphous indium–gallium–zinc oxide thin film transistors. It is observed that the charges trapped after electron injection in the interface and bulk traps are unstable and slowly decay over time. The stretched-exponential equation, which can be derived based on the trapping/detrapping of charges to/from existing traps and continuous redistribution of charges in bulk dielectrics, is successfully applied in fitting the time dependence of the threshold voltage shift during the stress and recovery phases under dynamic stresses. The characteristic time constants decrease with increasing temperature and drain bias during the recovery phase. Under dynamic stresses with various frequencies, the threshold voltage shift strongly depends on the frequency of dynamic stresses, i.e., a high frequency stress results in a small threshold voltage shift and a long lifetime. The stress-induced threshold shift phenomenon is observed to be relieved after a long-time low temperature post thermal annealing process and device passivation with an aluminum oxide layer.

Electron detrapping characteristics in positive bias temperature stressed n-channel metal-oxide-semiconductor field-effect transistors with ultrathin HfSiON gate dielectrics

Electrons trapped in the HfSiON gate dielectrics of n-channel metal-oxide-semiconductor field-effect transistors induced by positive bias temperature stress start to decay when the stress is interrupted or an opposite (recovery) voltage is applied. The decay begins with a quick detrapping within tens of nanoseconds followed by a slow detrapping. The quick detrapping depends on the recovery voltage and the trapping history, whereas the slow detrapping obeys approximately a logarithmic dependence on time with an almost identical slope before saturation. The observed detrapping behavior can be explained by a spatial and/or energetic distribution of trapped electrons in the HfSiON film. The device degradation under various dynamic stresses is found to be almost independent of frequency ranging from 0.001to1MHz, while it is slightly enhanced at 10MHz, probably due to insufficient recovery at the recovering half cycle.

Advanced Air Gap Process for Multi-Level-Cell Flash Memories Reducing Threshold Voltage Interference and Realizing High Reliability

As the cell size of flash memories is scaled down, the reading error due to threshold voltage (Vth) interference has become a more serious problem, particularly in the case of multi-level-cell (MLC) flash memories, it is necessary for the Vth distribution to be narrower than that of the single-level-cell (SLC). In this work, we propose an advanced air gap structure and process to reduce the interference due to the capacitance between floating gate and floating gate. By applying an air gap between neighboring floating gates as a lowest-dielectric-constant material, we can suppress Vth interference markedly. In addition, we clarified the correlation between the air gap forming process and the memory cell reliability. Hydrogen included in the SiO2 film, which is deposited by plasma-enhanced chemical vapor deposition (CVD) during air gap formation causes the degradation of memory cell endurance and the de-trapping characteristics. We were able to achieve a high-reliability memory cell by reducing the hydrogen concentration in the SiO2 by optimizing the deposition process for air gap formation.

Transient bicarrier response in high-k dielectrics and its impact on transient charge effects in high-k complementary metal oxide semiconductor devices

In this letter, transient charge trapping and detrapping characteristics in high-k n∕p metal oxide semiconductor field effect transistors (MOSFETs) were studied. Transient charge trapping was found to be an interface thickness-limited phenomenon. Additionally, transient trapping of electrons, rather than holes, was found to be dominant even in pMOSFETs. Transient charge recombination or bicarrier response within the high-k layer was the main reason for the dependence on input signal in high-k devices. Detrapping characteristics for nMOSEFTs and pMOSFETs were correlated to the transient hole and electron trappings, respectively.

Charge trapping and detrapping characteristics in hafnium silicate gate dielectric using an inversion pulse measurement technique

Threshold voltage (VTH) instability in metal oxide semiconductor field transistors (MOSFETs) with high dielectric constant (k) gate dielectrics has been investigated with an inversion pulse measurement technique, which can detect fast dielectric charging/discharging within microseconds (μs). The results indicate that VTH instability can be significantly underestimated by conventional VTH measurement techniques. Based on temperature-dependent stress data, it is suggested that charging and discharging are determined by direct tunneling and thermally assisted processes, respectively.

Trapping/De-Trapping Gate Bias Dependence of Hf-Silicate Dielectrics with Poly and TiN Gate Electrode

Constant voltage stress induced Vth shift and its detrapping characteristics under the negative gate bias has been extensively investigated with HF-silicate dielectrics with poly and TiN gate electrode. The threshold voltage shift in negative-channel metal-oxide semiconductor (NMOS) transistors under the positive gate bias stress is found to be associated mostly with the reversible electron trapping. A proper negative bias can be used to de-trap the electrons accumulated during the positive stress. However, an aggressive de-trapping can cause an additional Vth instability due to the excessive de-trapping of existing charge or additional hole trapping at the interface with poly gate. TiN metal gate is found to be more stable with de-trapping negative gate bias. To de-trap the electrons accumulated in the dielectric during the positive constant voltage stress (CVS), the negative bias and its duration should be chosen very carefully to avoid the additional charging associated with the hole trapping.

Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress

The V/sub th/ instability of nMOSFET with HfSiON gate dielectric under various stress conditions has been evaluated. It is shown that after constant voltage stress, the threshold voltage (V/sub th/) relaxes to its initial prestress value. The relaxation rate is strongly affected by the stress duration and magnitude rather than injected charge flux or magnitude of the V/sub th/ shift. It is proposed that spatial distribution of trapped charges, which is strongly affected by the stress conditions, determines the relaxation rate. The implications of the electron trapping/detrapping processes on electrical evaluation of the high-/spl kappa/ gate dielectrics are discussed.