Design Space Exploration Research Articles

A Clock Tree Prediction and Optimization Framework Using Generative Adversarial Learning

Modern physical design flows highly depend on design space exploration to find the commercial tools’ clock tree synthesis (CTS) parameters that lead to optimized clock trees. However, such exploration is often time-consuming and computationally inefficient. In this article, we overcome this drawback by proposing a novel framework named GAN-CTS, which utilizes conditional generative adversarial network (GAN) to predict and optimize CTS outcomes. Our framework is built upon three sequential learning stages. First, to precisely characterize distinct designs, we leverage transfer learning to extract netlist features directly from placement images. Second, we perform regression learning using various methods to predict the target CTS outcomes and demonstrate that the proposed multitask learning approach achieves better accuracy than the meta-modeling method adopted by previous works. To fully benefit from the predictions made by our framework, we further quantitatively interpret the importance of each CTS input parameter subject to various design objectives through attribution-based learning. Finally, generative adversarial learning is leveraged to optimize the target clock metrics with the guidance provided by the pretrained regression model. To substantiate the generality of our framework, we perform validations on four unseen netlists that are not utilized in the training process. The experimental results conducted on real-world designs demonstrate that our framework: 1) achieves an average prediction error of 3%; 2) improves the commercial tool’s auto-generated clock tree by 20.7% in clock power, 21.5% in clock wirelength, 36.1% in the worst skew; and 3) reaches an F1-score of 0.93 in the classification task of determining successful and failed CTS runs.

Fast Large-Integer Extended GCD Algorithm and Hardware Design for Verifiable Delay Functions and Modular Inversion

The extended GCD (XGCD) calculation, which computes Bézout coefficients ba, bb such that ba ∗ a0 + bb ∗ b0 = GCD(a0, b0), is a critical operation in many cryptographic applications. In particular, large-integer XGCD is computationally dominant for two applications of increasing interest: verifiable delay functions that square binary quadratic forms within a class group and constant-time modular inversion for elliptic curve cryptography. Most prior work has focused on fast software implementations. The few works investigating hardware acceleration build on variants of Euclid’s division-based algorithm, following the approach used in optimized software. We show that adopting variants of Stein’s subtraction-based algorithm instead leads to significantly faster hardware. We quantify this advantage by performing a large-integer XGCD accelerator design space exploration comparing Euclid- and Stein-based algorithms for various application requirements. This exploration leads us to an XGCD hardware accelerator that is flexible and efficient, supports fast average and constant-time evaluation, and is easily extensible for polynomial GCD. Our 16nm ASIC design calculates 1024-bit XGCD in 294ns (8x faster than the state-of-the-art ASIC) and constant-time 255-bit XGCD for inverses in the field of integers modulo the prime 2255−19 in 85ns (31× faster than state-of-the-art software). We believe our design is the first high-performance ASIC for the XGCD computation that is also capable of constant-time evaluation. Our work is publicly available at https://github.com/kavyasreedhar/sreedhar-xgcd-hardware-ches2022.

System Analysis and Design Space Exploration of Regional Aircraft with Electrified Powertrains

This paper explores the design spaces of a thin-haul and a regional aircraft with parallel hybrid-electric propulsion architectures for a 2030 entry into service date. Notional technology reference aircraft models were developed for a 19- and a 50-passenger aircraft based on publicly available data on Beechcraft 1900D and ATR 42-600, respectively. A set of airframe and propulsion system technologies projected to reach maturity by 2030 was infused into the aircraft models. Parametric, physics-based models were created for the charge-depleting hybrid architecture. Different modes of operation were identified and parameterized with a range of design variables to investigate the feasibility and trade space for peak power shaving, climb power boosting, electric taxi, battery usage schedules, and in-flight battery recharge strategies. Thousands of electrified aircraft concepts with varying electrification, operation, and technology scenarios were sized under the same system-level requirements as their conventional counterpart. The resulting multidisciplinary design space exploration environment was used to identify the optimum vision system designs and modes of operation for the minimum block fuel-burn objective. It has been found that both vehicle classes with the charge-depleting parallel hybrid electric architecture provided fuel-burn benefits over their 2030 advanced technology counterparts under certain operational modes.

Towards Modelica Models with Credibility Information

Modeling and simulation is increasingly used in the design process for a wide span of applications. Rising demands and the complexity of modern products also increase the need for models and tools capable to cover areas such as virtual testing, design-space exploration or digital twins, and to provide measures of the quality of the models and the achieved results. The latter is also called credible simulation process. In an article at the International Modelica Conference 2021, we summarized the state of the art and best practice from the viewpoint of a Modelica language user, based on the experience gained in projects in which Modelica models were utilized in the design process. Furthermore, missing features and gaps in the used processes were identified. In this article, new proposals are presented to improve the quality of Modelica models, in particular by adding traceability, uncertainty, and calibration information of the parameters in a standardized way to Modelica models. Furthermore, the new open-source Modelica library Credibility is discussed together with examples to support the implementation of credible Modelica models.

Software tools to enable immersive simulation

There are two main avenues to design space exploration. In the first approach, a simulation is run, analyzed, the problem modified, and the simulation run again. In the second approach, an ensemble simulation is performed and the battery of results is leveraged to construct a surrogate model for a given quantity of interest (QoI). The first approach allows a practitioner to methodically move through the design space and analyze a solution field. A disadvantage of this technique is that each new simulation requires time-consuming setup. The second approach provides the practitioner with a global view of the problem, but requires a priori design space limits and the QoI specification. In this work, we introduce an immersive simulation software framework that enables practitioners to maintain the flexibility of the first approach, while eliminating the burden of setting up new simulations. Immersive simulation can also be used to inform the second approach, establishing limits and clarifying QoI selection prior to the launch of an ensemble simulation. We demonstrate live, reconfigurable visualization of on-going simulations coupled with live, reconfigurable problem definition that guides users in determining problem parameters. Ultimately, an immersive simulation framework enables more efficient design space exploration that reduces the gap between simulations, data analysis, and insight extraction.

Toward Holistic Design of Spatial Packaging of Interconnected Systems With Physical Interactions (SPI2)

Abstract Three-dimensional spatial packaging of interconnected systems with physical interactions (SPI2) design plays a vital role in the functionality, operation, energy usage, and life cycle of practically all engineered systems, from chips to ships. SPI2 design problems are highly nonlinear, involving tightly constrained component placement, governed by coupled physical phenomena (thermal, hydraulic, electromagnetic, etc.), and involve energy and material transfer through intricate geometric interconnects. While many aspects of engineering system design have advanced rapidly in the last few decades through breakthroughs in computational support, SPI2 design has largely resisted automation and in practice requires at least some human-executed design steps. SPI2 system reasoning and design decisions can quickly exceed human cognitive abilities at even moderate complexity levels, thwarting efforts to accelerate design cycles and tackle increasingly complex systems. Existing design methods treat pieces of the SPI2 problem separately without a fundamental systems approach, are sometimes inefficient to evaluate various possible designs, and present barriers to effective adoption in practice. This article explores a vision of a holistic SPI2 design approach needed to develop next-generation automated design methods capable of rapidly producing viable SPI2 design candidates. We review several technical domains related to holistic SPI2 design, discuss existing knowledge gaps and practical challenges, examine exciting opportunities at the intersection of multiple domains that can enable comprehensive exploration of SPI2 design spaces, and present one viable two-stage SPI2 design automation framework. Holistic SPI2 design opens up a new direction of high industrial and societal relevance for the design research community.

Don't Let Your Constraints Constrain You – Towards Design Space Exploration with Flexible Constraints for Flow Sheet Simulations

Don't Let Your Constraints Constrain You – Towards Design Space Exploration with Flexible Constraints for Flow Sheet Simulations

Efficient reliability analysis using prediction-oriented active sparse polynomial chaos expansion

In this paper, a prediction-oriented active sparse polynomial chaos expansion (PAS-PCE) is proposed for reliability analysis. Instead of leveraging on additional techniques to reduce the problem dimensionality and/or to obtain the local error estimates, which has been done in the majority of existing PCE-based methods, this study first makes use of the Bregman-iterative greedy coordinate descent in effectively solving the least absolute shrinkage and selection operator based regression for sparse PCE approximation with a small set of initial samples. Then, the local variance distribution of the performance function is predicted using the approximated PCE. By maximizing an optimality measure that balances the exploration of design space and exploitation of the PCE characteristics, a recently proposed learning function is subsequently adopted for selecting the optimal samples one by one from a candidate pool to cover the limit state surface regions proportionally to the predicted local variance. The performance of the proposed PAS-PCE is assessed on four numerical examples of varying complexity and input dimensionality through comparison with several state-of-the-art active learning methods based on a variety of surrogate models. Results show that the proposed method is superior to the benchmark algorithms in terms of both accuracy and efficiency for reliability analysis.

Rapid and Accurate PPA Prediction for the Template-Based Processor Design Methods

The template-based chip design method aims to build rapidly. However, it still need synthesis and simulation flows to get the performance, power, and area (PPA) reports and find the proper parameters set in the design space exploration, which takes a long time. Therefore, a rapid and accurate PPA prediction method is proposed. At first, the PPA Prediction Model based on Multivariate Linear regression (ML-PM) is proposed to fit the multiple parameters’ influence on the PPA via the single parameter affection. Moreover, a Multivariate NonLinear regression Prediction Model (MNL-PM) based on Amdahl’s law is introduced to improve the accuracy of the PPA estimation. The empirical evaluation of the method shows that the PPA prediction for the template-based chip design methods can reach 98.60%, 99.19%, and 98.53% accuracy on performance, power, and, area separately, when compared with the PPA generated via the synthesis and simulation flows.

Cascade Structural Sizing Optimization with Large Numbers of Design Variables

In structural sizing optimization problems, the number of design variables typically used is relatively small. The aim of this work is to facilitate the use of large numbers of design variables in such problems, in order to enrich the set of available design options and offer the potential of achieving lower-cost optimal designs. For this purpose, the concept of cascading is employed, which allows an optimization problem to be tackled in a number of successive autonomous optimization stages. In this context, several design variable configurations are constructed, in order to utilize a different configuration at each cascade sizing optimization stage. Each new cascade stage is coupled with the previous one by initializing the new stage using the finally attained optimum design of the previous one. The first optimization stages of the cascade procedure make use of the coarsest configurations with small numbers of design variables and serve the purpose of basic design space exploration. The last stages exploit finer configurations with larger numbers of design variables and aim at fine-tuning the achieved optimal solution. The effectiveness of this sizing optimization approach is assessed using real-world aerospace and civil engineering design problems. Based on the numerical results reported herein, the proposed cascade optimization approach proves to be an effective tool for handling large numbers of design variables and the corresponding extensive design spaces in the framework of structural sizing optimization applications.

Structural optimization of the wing box for a hybrid-electric commuter aircraft

Hybrid-electric commuter aircraft segment is playing a significant role in the electrification of air transportation. Towards the achievement of efficient and robust transportation, design and optimization processes are necessary to evaluate the different aircraft components. Within this context, the current work investigates the impact of the positioning of the propulsion system and spars on the structural integrity of a hybrid-electric commuter aircraft. The proposed approach is based on an in-house aircraft sizing tool, along with geometry generation and high-fidelity structural evaluation models. These tools are tailored in an automated computational pipeline, that includes pre-processing, model evaluation and post-processing tasks, able to perform design space exploration and optimization over different loading conditions of a selected mission envelope. This work focuses on the assessment of the impact of the additional non-structural weight e.g., batteries, fuel, and propulsion components, inside the wing box, on the stress, deformation and spanwise thickness distribution of the structure. The effect of spars and propulsion system positioning on the available storage space, maximum stress and displacement is discussed, with the aft spar having the greatest impact. Finally, the structural model is optimized to minimize the mass, resulting in a 29% weight reduction, compared to the initial design.

A Comprehensive Methodology to Optimize FPGA Designs via the Roofline Model

With reconfigurable fabrics delivering increasing performance over the years, Field-Programmable Gate Arrays (FPGAs) are becoming an appealing solution for next-generation High-Performance Computing (HPC) systems. However, in order to gain traction among traditional von Neumann architectures, the optimization process of Field-Programmable Gate Array (FPGA) designs should be further abstracted to a higher level. In fact, while High-Level Synthesis (HLS) already provides a handy way to write FPGA code with common high-level languages, substantial effort and expertise are still required to optimize the resulting FPGA design for the underlying hardware. To overcome this problem, we propose a semi-automated performance optimization methodology based on a Hierarchical Roofline model for FPGAs. System-wide and applications-specific optimizations such as off-chip memory transfer and data locality optimizations are guided by the FPGA Roofline model whereas FPGA-specific optimizations are automatically searched by a Design Space Exploration (DSE) engine. We demonstrate the way this methodology allows to easily analyze and optimize to peak system performance a wide set of applications ranging from particle methods, wavefront algorithms, and sparse arithmetic computations. In addition, we prove that the integrated Design Space Exploration (DSE) engine achieves a 14.36x maximum speedup if compared to previous automated solutions in the literature.

A machine learning accelerated inverse design of underwater acoustic polyurethane coatings

Here we propose a detailed protocol to enable an accelerated inverse design of acoustic coatings for underwater sound attenuation application by coupling Machine Learning and an optimization algorithm with Finite Element Models (FEM). The FEMs were developed to obtain the realistic performance of the polyurethane (PU) acoustic coatings with embedded cylindrical voids. The frequency dependent viscoelasticity of PU matrix is considered in FEM models to substantiate the impact on absorption peak associated with the embedded cylinders at low frequencies. This has been often ignored in previous studies of underwater acoustic coatings, where usually a constant frequency-independent complex modulus was used for the polymer matrix. The key highlight of the proposed optimization framework for the inverse design lies in its potential to tackle the computational hurdles of the FEM when calculating the true objective function. This is done by replacing the FEM with an efficiently computable surrogate model developed through a Deep Neural Network. This enhances the speed of predicting the absorption coefficient by a factor of 4.5 times 10^3 compared to FEM model and is capable of rapidly providing a well-performing, sub-optimal solution in an efficient way. A significant, broadband, low-frequency attenuation is achieved by optimally configuring the layers of cylindrical voids. This is accomplished by accommodating attenuation mechanisms, including Fabry–Pacute{e}rot resonance and Bragg scattering of the layers of voids. Furthermore, the proposed protocol enables the inverse and targeted design of underwater acoustic coatings through accelerating the exploration of the vast design space compared to time-consuming and resource-intensive conventional trial-and-error forward approaches.

High-Speed Adder Design Space Exploration via Graph Neural Processes

Adders are the primary components in the data-path logic of a microprocessor, and thus, adder design has been always a critical issue in the very large-scale integration (VLSI) industry. However, it is infeasible for designers to obtain optimal adder architecture by exhaustively running EDA flow due to the extremely large design space. Previous arts have proposed the machine learning-based framework to explore the design space. Nevertheless, they fall into suboptimality due to a two-stage flow of the learning process and less efficient nor effective feature representations of prefix adder structures. In this article, we first integrate a variational graph autoencoder and a neural process (NP) into an end-to-end, multibranch framework, which is termed the <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">graph neural process</i> . The former performs automatic feature learning of prefix adder structures, whilst the latter one is designed as an alternative to the Gaussian process. Then, we propose a sequential optimization framework with the graph NP as the surrogate model to explore the Pareto-optimal prefix adder structures with tradeoff among Quality-of-Result (QoR) metrics, such as power, area, and delay. The experimental results show that compared with state-of-the-art methodologies, our framework can achieve a much better Pareto frontier in multiple QoR metric spaces with fewer design-flow evaluations.

Compiling All-Digital-Embedded Content Addressable Memories on Chip for Edge Application

A spectrum of emerging applications, including edge artificial intelligence, advocates the precompute-and-search scheme with embedded small-size content addressable memory (CAM) for its hardware efficiency instead of repetitive arithmetic operations. However, the integration of the CAM macros that are conventionally implemented with full custom analog circuits renders design-space exploration and optimization to be difficult at system level. As an alternative, a complete design flow for compiling ternary CAM on chip using foundry-supplied digital standard cells is introduced in this article. Based on the novel CAM architecture and logic design, we leverage guided placement and routing with mainstream EDA tools for exploiting the inherent structure regularity of CAM-cell arrays in the layout. An analytical model is also presented, which allows us for a systematic investigation on the energy reduction by adapting our design to various presearch structures. Validated on a postlayout <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32{\times }64$ </tex-math></inline-formula> ternary CAM in 28 nm, our parallel-matching scheme performs at 2.6 GHz with 0.42 fJ/bit/search, and the (8-bit) presearch scheme achieves 0.19 fJ/bit/search at 1.1 GHz, both under the 0.9-V supply voltage. In addition to flexibility for tradeoffs between the search throughput and energy, our all-digital CAM design enables voltage scaling aggressively down to 0.45 V with a minimum energy consumption of 0.06 fJ/bit/search at 50 MHz.

Multi-scale rotation-equivariant graph neural networks for unsteady Eulerian fluid dynamics

The simulation of fluid dynamics, typically by numerically solving partial differential equations, is an essential tool in many areas of science and engineering. However, the high computational cost can limit application in practice and may prohibit exploring large parameter spaces. Recent deep-learning approaches have demonstrated the potential to yield surrogate models for the simulation of fluid dynamics. While such models exhibit lower accuracy in comparison, their low runtime makes them appealing for design-space exploration. We introduce two novel graph neural network (GNN) models, multi-scale (MuS)-GNN and rotation-equivariant (RE) MuS-GNN, for extrapolating the time evolution of the fluid flow. In both models, previous states are processed through multiple coarsening of the graph, which enables faster information propagation through the network and improves the capture and forecast of the system state, particularly in problems encompassing phenomena spanning a range of length scales. Additionally, REMuS-GNN is architecturally equivariant to rotations, which allows the network to learn the underlying physics more efficiently, leading to improved accuracy and generalization. We analyze these models using two canonical fluid models: advection and incompressible fluid dynamics. Our results show that the proposed GNN models can generalize from uniform advection fields to high-gradient fields on complex domains. The multi-scale graph architecture allows for inference of incompressible Navier–Stokes solutions, within a range of Reynolds numbers and design parameters, more effectively than a baseline single-scale GNN. Simulations obtained with MuS-GNN and REMuS-GNN are between two and four orders of magnitude faster than the numerical solutions on which they were trained.

Prediction Modeling for Application-Specific Communication Architecture Design of Optical NoC

Multi-core systems-on-chip are becoming state-of-the-art. Therefore, there is a need for a fast and energy-efficient interconnect to take full advantage of the computational capabilities. Integration of silicon photonics with a traditional electrical interconnect in a Network-on-Chip (NoC) proposes a promising solution for overcoming the scalability issues of electrical interconnect. In this article, we derive and evaluate prediction modeling techniques for the design space exploration (DSE) of application-specific communication architectures for an Optical Network-on-Chip (ONoC). Our proposed model accurately predicts network packet latency, contention delay, and the static and dynamic energy consumption of the network. This work specifically addresses the challenge of accurately estimating performance metrics of the entire design space without having to perform time-consuming and computationally intensive exhaustive simulations. The proposed technique, based on machine learning (ML), can build accurate prediction models using only 10% to 50% (best case and worst case) of the entire design space. The accuracy, expressed as R 2 (Coefficient of Determination) is 0.99901, 0.99967, 0.99996, and 0.99999 for network packet latency, contention delay, static energy consumption, and dynamic energy consumption, respectively, in six different benchmarks from the Splash-2 benchmark suite, chosen among 6 different machine learning prediction models.

Improve Syntax Correctness and Breadth of Design Space Exploration in Functional Analysis

Abstract Functional analysis aims to decompose the main functions of a product, which can be large and complex, into more manageable subfunctions. Recently, interest in explicitly considering users during functional modeling has grown to enhance analysis completeness, but how this addresses some commonly reported challenges for novice engineers is not clear. This research proposes and assesses a simple way to streamline user considerations in functional analysis as potential mitigation for some challenges (i.e., difficulty in identifying functions to explore design space and expressing the functions with expected syntax and solution neutrality) that novice designers frequently mention at the early design stage. Analysis of the results indicates that embedding requirements into a user workflow supports novice designers generate significantly more functions with correct syntax than starting with requirements only. In addition, the exploration space is prominently broader, especially at the higher levels measured by the geometry of the generated hierarchical models. These results suggest that strategically incorporating user considerations, even in a simple way, positively addresses the common challenges. This initial exploration and assessment could serve as an inspiration for future research on more efficient ways to streamline the functional decomposition process and, in turn, better support subsequent systematic conceptual design.

Evaluation of gem5 for performance modeling of ARM Cortex-R based embedded SoCs

ARM CPUs are prevalent in embedded systems ranging from low-power IoT to reasonably high-powered mobile phones and devices. Embedded SoCs integrate a number of accelerators with CPUs to achieve the tight performance and power budget. To overcome the challenges of architecting these complex SoCs, designers employ performance simulators as a design space exploration tool. Developing such a simulator infrastructure in itself is challenging and depends on accurately modeling the ARM CPUs and the interaction of various accelerators with the CPU. The widely used, open-source gem5 simulator provides the necessary components to develop such an infrastructure in a time and cost-effective manner. In this paper, we present the limit study and evaluation of using gem5 for building a performance modeling and analysis framework targeted to ARM R series CPU-based embedded SoC. First, we illustrate the approach to develop the framework by tuning the extensive configuration space of gem5 and making modifications for new features. We consider different CPUs, branch predictors, memory modules, and SystemC coupling in gem5. Second, we perform a detailed correlation of the simulator with a real ARM CPU and explain the shortcomings, challenges, and ways to improve the accuracy. We obtain average absolute errors of 13% for the Embench suite Bennett et al. (2019). We also point out large miscorrelations for specific pattern in ALU (50%), Branch (135%) and Memory (35%). Finally, through a case study to design a flexible NVMe SSD controller architecture, we demonstrate the framework’s design space exploration capabilities.

A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor

A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor