Design Space Exploration Research Articles

An FPGA-based memristor emulator for artificial neural network

Emulating memristor via FPGA offers flexibility for quick prototyping and design space exploration because memristor manufacture and integration are currently insufficient for large-scale application in neural networks. Although important, the creation of fast and lightweight FPGA memristor emulators is still very difficult. In this work, a reconfigurable memristor emulator that can be implemented in digital circuits is proposed. With less than 1% hardware utilization and a 258 MHz operating frequency, the suggested solution has been successfully synthesized and confirmed on a Xilinx ZYNQ-7000 FPGA. Additionally, this work builds a memristor crossbar array for extracting digital picture information and then performs the digital recognition task using a quantitative artificial neural network in order to assess the synaptic function of the suggested memristor model. The experimental results show that the recognition accuracy of MNIST dataset images by the memristor network circuit reaches 91.89%.

Holistic Approach to Ship Design

The recently completed Horizon 2020 European Research project—HOLISHIP—Holistic Optimization of Ship Design and Operation for Life Cycle (2016–2020) has developed suitable tools and software platforms which are necessary for the creation of innovative design solutions meeting the set low-emission strategic objectives. The present paper introduces an innovative, holistic approach to ship design and the development of integrated design software platforms and tools, which are used in practical applications. In the era of the 4th industrial revolution, this project sets out to substantially advance ship design via the introduction of a fully computerized, multi-disciplinary optimization approach to ship design and life-cycle operation. The approach enables the exploration of a huge design space in a relatively short time, as well as the distributed/multi-site working and the virtual reality testing; thus, it is a strong asset for the development of innovative maritime concepts in response to the needs of the 21st century.

Compositionality in Computational Linguistics

Neural models greatly outperform grammar-based models across many tasks in modern computational linguistics. This raises the question of whether linguistic principles, such as the Principle of Compositionality, still have value as modeling tools. We review the recent literature and find that while an overly strict interpretation of compositionality makes it hard to achieve broad coverage in semantic parsing tasks, compositionality is still necessary for a model to learn the correct linguistic generalizations from limited data. Reconciling both of these qualities requires the careful exploration of a novel design space; we also review some recent results that may help in this exploration.

On Transferring Application Mapping Knowledge Between Differing MPSoC Architectures

The mapping of soft real-time applications onto a heterogeneous MPSoC target architecture is of high importance for meeting deadlines and minimizing secondary objectives like the consumed energy on the platform. In particular, for applications with input-dependent workload variation, hybrid application mapping (HAM) has crystallized itself as the state-of-the-art mapping approach that combines time-intensive design space exploration with lightweight run-time management. However, one general problem of HAM is that the explored mappings and models are highly specific to a certain target architecture. If the architecture is modified or changed (e.g., due to hardware upgrades, downgrades, or architectural degradation), the design-time optimization has to be repeated once again, which might take up to multiple weeks. As a remedy, this article proposes a twofold mapping transfer methodology that speeds up the design-time optimization for a novel or modified target architecture based on the knowledge we gained from the optimization for the original source architecture. First, we describe a greedy mapping transfer heuristic that provides feasible mappings for the new architecture in negligible optimization time. Second, we present a mapping refinement heuristic that improves these mappings even further while needing only a fraction of the optimization time of state-of-the-art approaches. As we show in the evaluation section, our approach can drastically speed up the convergence of the optimization for the novel architecture even if the sizes of the original and novel target architecture or the characteristics of the used resources differ significantly. Note that our approach assumes that the source and target architectures are both tile-based Network-on-Chip (NoC) meshes.

STC Short-Circuit Current Prediction and I–V Simulation of Colored BIPV Modules With Machine Learning and One-Diode Equivalent Circuit Models

Colored photovoltaic (PV) modules offer improved aesthetics at the cost of electrical performance loss. Here, we demonstrate a hybrid approach combining experiments, machine learning, and equivalent-circuit model to predict and simulate <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I–V</i> parameters of colored crystalline-silicon PV modules. First, to predict the short-circuit current for different colors and opacity levels, three models—multiple linear regression (MLR), optimized support vector regression (SVR), and optimized Gaussian process regression (GPR)—are trained and evaluated with a ten-fold cross validation. The MLR model shows an MAE = 3.58 and an RMSE = 5.17. The accuracy could be further improved with the more advanced models, i.e., an optimized SVR (MAE = 0.22, RMSE = 0.24) or an optimized GPR (MAE = 0.13, RMSE = 0.17). Following, by taking the predicted short-circuit current values as inputs into a one-diode equivalent circuit model, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I–V</i> curves of two multicolored modules are simulated; and information such as module power <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">P</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mpp</sub> and current mismatch loss are extracted. There is a twofold advantage of implementing our approach: first, it serves as an efficient design space exploration methodology for a wide parameter space (e.g., colors), i.e., evaluating the PV performance for new colors without samples fabrication, thus saving time and resources; and second, it guides architects, designs, and engineers in color/design selection to achieve a balance between aesthetics and engineering considerations.

Analysis of Power Delivery Network (PDN) in Bridge-Chips for 2.5-D Heterogeneous Integration

In this article, we investigate the impact of power delivery network (PDN) in bridge-chip-based 2.5/3-D heterogeneous integration platforms. The focus of the article is bridge-chip-based central processing unit (CPU)-field-programmable gate array (FPGA) and FPGA-stacked memory integration technologies. While bridge-chip-based interconnect platforms present PDN challenges, depending on the power map, including a PDN in the bridge-chip can help reduce the impact significantly. We perform three case studies: 1) inclusion of ground network in the bridge-chip; 2) inclusion of power and ground network in the bridge-chip; and 3) inclusion of metal-insulator-metal (MIM) decoupling capacitors in the bridge-chip. Inclusion of both power and ground network can reduce DC IR drop by ~20% for a CPU-FPGA integration case study and by ~40% for an FPGA-stacked memory configuration. Our <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L (di/dt)$ </tex-math></inline-formula> noise analysis shows that if we include decoupling capacitors in the bridge-chip, we can significantly reduce the high-frequency ripple in the power supply. We also perform a design space exploration for power delivery with the following parameters: 1) resistance of the PDN in the bridge-chip; 2) decoupling capacitor density in the bridge-chip; and 3) overlap region between a bridge-chip and active dice.

Energy-Quality Scalable Design Space Exploration of Approximate FFT Hardware Architectures

This paper presents a comprehensive design space exploration for boosting energy efficiency of a fast Fourier transform (FFT) VLSI accelerator, exploiting several approximate multipliers (AxM) combined with approximate adder (AxA) circuits. The FFT hardware herein presented consists of a fixed-point sequential architecture using a radix-2 butterfly with decimation in time. We explore a set of AxMs – namely Dynamic Range Unbiased (DRUM), Rounding-based Approximate (RoBA), leading one Bit-based Approximate (LoBA), and Truncated approach – jointly with the LOA, ETA-I, CopyA, CopyB, Trunc0, Trunc1 approximate adders. The approximate arithmetic operators are used in the butterfly kernel with exploration of the approximation levels (for the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${K}$ </tex-math></inline-formula> least-significant bits, respectively, for the AxM and AxA), aiming at discovering the most energy-efficient configuration under a design-time QoR constraint. The mean square error and peak signal-to-noise ratio metrics define which approximate levels combining <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${K}$ </tex-math></inline-formula> variations will enable the FFT to process signals to generate spectrograms without significant losses. Our results show that the LoBA multiplier with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$L$ </tex-math></inline-formula> =8 together with the LOA, Trunc1 and Trunc0, at different approximation levels, provide most energy savings with controllable quality degradation, presenting a minimum decrease of 20.2% in power dissipation without degrading the spectrogram generation quality.

Design Space Exploration of Practical VVC Encoding for Emerging Media Applications

Versatile Video Coding (VVC/H.266) is the latest video coding standard designed for a broad range of next-generation media applications. This paper explores the design space of practical VVC encoding by profiling the Fraunhofer Versatile Video Encoder (VVenC). All experiments were conducted over five 2160p video sequences and their downsampled versions under the random access (RA) condition. The exploration was performed by analyzing the rate-distortion-complexity (RDC) of the VVC block structure and coding tools. First, VVenC was profiled to provide a breakdown of coding block distribution and coding tool utilization in it. Then, the usefulness of each VVC coding tool was analyzed for its individual impact on overall RDC performance. Finally, our findings were elevated to practical implementation guidelines: the highest coding gains come with the multi type tree (MTT) structure, adaptive loop filter (ALF), cross component linear model (CCLM), and bi-directional optical flow (BDOF) coding tools, whereas multi transform selection (MTS) and affine motion estimation are the primary candidates for complexity reduction. To the best of our knowledge, this is the first work to provide a comprehensive RDC analysis for practical VVC encoding. It can serve as a basis for practical VVC encoder implementation or optimization on various computing platforms.

Descriptor Aided Bayesian Optimization for Many-Level Qualitative Variables With Materials Design Applications

Abstract Engineering design often involves qualitative and quantitative design variables, which requires systematic methods for the exploration of these mixed-variable design spaces. Expensive simulation techniques, such as those required to evaluate optimization objectives in materials design applications, constitute the main portion of the cost of the design process and underline the need for efficient search strategies—Bayesian optimization (BO) being one of the most widely adopted. Although recent developments in mixed-variable Bayesian optimization have shown promise, the effects of dimensionality of qualitative variables have not been well studied. High-dimensional qualitative variables, i.e., with many levels, impose a large design cost as they typically require a larger dataset to quantify the effect of each level on the optimization objective. We address this challenge by leveraging domain knowledge about underlying physical descriptors, which embody the physics of the underlying physical phenomena, to infer the effect of unobserved levels that have not been sampled yet. We show that physical descriptors can be intuitively embedded into the latent variable Gaussian process approach—a mixed-variable GP modeling technique—and used to selectively explore levels of qualitative variables in the Bayesian optimization framework. This physics-informed approach is particularly useful when one or more qualitative variables are high dimensional (many-level) and the modeling dataset is small, containing observations for only a subset of levels. Through a combination of mathematical test functions and materials design applications, our method is shown to be robust to certain types of incomplete domain knowledge and significantly reduces the design cost for problems with high-dimensional qualitative variables.

Design space exploration for balanced MLC-PCM programming

Multi-Level Cell Phase Change Memory (MLC PCM) is a non-volatile memory technology that promises high-density data storage. However, MLC PCM suffers from long write latency because changing the state of each memory cell takes a long time and the number of cells that can be written concurrently is limited due to the relatively large size and power consumption of the write drivers. MLC PCM typically divides the write data into multiple cell groups to program cells in batches. The group mapping has a significant impact on the overall latency of write requests. Prior work proposed a group mapping technique for single-level cell (SLC) PCM based on the data pattern of a set of applications. In this work, a larger design space of group mapping is explored for MLC PCM. The specific group mapping for each benchmark is dynamically customized. Our technique leads to a 13.14% reduction in write latency compared to the state-of-the-art method (Du et al., 2013) and shows good temporal consistence in different benchmarks.

K-Periodic Scheduling for Throughput-Buffering Trade-Off Exploration of CSDF

The design of time-critical embedded systems often requires static models of computation such as cyclo-static dataflow. These models enable performance guarantees, execution correctness, and optimized memory usage. Nonetheless, determining optimal buffer sizing of dataflow applications remains difficult: existing methods offer either approximate solutions or fail to provide solutions for complex instances. We propose a throughput-buffering trade-off exploration that uses K-periodic scheduling to direct a design-space exploration—providing optimal solutions while significantly reducing the search space compared to existing methodologies. We compare this strategy against previous approaches and demonstrate search-space reductions over two benchmark suites, resulting in significant improvements in computation times while retaining optimal results.

Monolithic TCAD simulation of phase-change memory (PCM/PRAM) + Ovonic Threshold Switch (OTS) selector device

Owing to the increasing interest in the commercialization of phase-change memory (PCM) devices, a number of TCAD models have been developed for their simulation. These models formulate the melting, amorphization and crystallization of phase-change materials as well as their extreme conductivity dependence on both electric field and temperature into a set of self-consistently-solved thermoelectric and phase-field partial-differential equations. However, demonstrations of the ability of such models to match actual experimental results are rare. In addition, such PCM devices also require a so-called selector device – such as an Ovonic Threshold Switching (OTS) device – in series for proper memory operation. However, monolithic simulation of both the PCM and OTS selector device in a single simulation is largely absent from the literature, despite its potential value for material- and design-space explorations. It is the goal of this work to first characterize a PCM device in isolation against experimental data, then to demonstrate the qualitative behavior of a simulated OTS device in isolation and finally to perform a single monolithic simulation of the PCM + OTS device within the confines of a commercially available TCAD solver: GTS Framework.

Atomistically-informed continuum modeling and isogeometric analysis of 2D materials over holey substrates

This work develops, discretizes, and validates a continuum model of a molybdenum disulfide (MoS2) monolayer interacting with a periodic holey silicon nitride (Si3N4) substrate via van der Waals (vdW) forces. The MoS2 layer is modeled as a geometrically nonlinear Kirchhoff–Love shell, and vdW forces are modeled by a Lennard-Jones (LJ) potential, simplified using approximations for a smooth substrate topography. Both the shell model and LJ interactions include novel extensions informed by close comparison with fully-atomistic calculations. The material parameters of the shell model are calibrated by comparing small-strain tensile and bending tests with atomistic simulations. This model is efficiently discretized using isogeometric analysis (IGA) for the shell structure and a pseudo-time continuation method for energy minimization. The IGA shell model is validated against fully-atomistic calculations for several benchmark problems with different substrate geometries. Agreement with atomistic results depends on geometric nonlinearity in some cases, but a simple isotropic St.Venant–Kirchhoff model is found to be sufficient to represent material behavior. We find that the IGA discretization of the continuum model has a much lower computational cost than atomistic simulations, and expect that it will enable efficient design space exploration in strain engineering applications. This is demonstrated by studying the dependence of strain and curvature in MoS2 over a holey substrate as a function of the hole spacing on scales inaccessible to atomistic calculations. The results show an unexpected qualitative change in the deformation pattern below a critical hole separation.

Hallucinating structure-conditioned antibody libraries for target-specific binders.

Antibodies are widely developed and used as therapeutics to treat cancer, infectious disease, and inflammation. During development, initial leads routinely undergo additional engineering to increase their target affinity. Experimental methods for affinity maturation are expensive, laborious, and time-consuming and rarely allow the efficient exploration of the relevant design space. Deep learning (DL) models are transforming the field of protein engineering and design. While several DL-based protein design methods have shown promise, the antibody design problem is distinct, and specialized models for antibody design are desirable. Inspired by hallucination frameworks that leverage accurate structure prediction DL models, we propose the FvHallucinator for designing antibody sequences, especially the CDR loops, conditioned on an antibody structure. Such a strategy generates targeted CDR libraries that retain the conformation of the binder and thereby the mode of binding to the epitope on the antigen. On a benchmark set of 60 antibodies, FvHallucinator generates sequences resembling natural CDRs and recapitulates perplexity of canonical CDR clusters. Furthermore, the FvHallucinator designs amino acid substitutions at the VH-VL interface that are enriched in human antibody repertoires and therapeutic antibodies. We propose a pipeline that screens FvHallucinator designs to obtain a library enriched in binders for an antigen of interest. We apply this pipeline to the CDR H3 of the Trastuzumab-HER2 complex to generate in silico designs predicted to improve upon the binding affinity and interfacial properties of the original antibody. Thus, the FvHallucinator pipeline enables generation of inexpensive, diverse, and targeted antibody libraries enriched in binders for antibody affinity maturation.

Assessing Deep Generative Models in Chemical Composition Space

The computational discovery of novel materials has been one of the main motivations behind research in theoretical chemistry for several decades. Despite much effort, this is far from a solved problem, however. Among other reasons, this is due to the enormous space of possible structures and compositions that could potentially be of interest. In the case of inorganic materials, this is exacerbated by the combinatorics of the periodic table since even a single-crystal structure can in principle display millions of compositions. Consequently, there is a need for tools that enable a more guided exploration of the materials design space. Here, generative machine learning models have recently emerged as a promising technology. In this work, we assess the performance of a range of deep generative models based on reinforcement learning, variational autoencoders, and generative adversarial networks for the prototypical case of designing Elpasolite compositions with low formation energies. By relying on the fully enumerated space of 2 million main-group Elpasolites, the precision, coverage, and diversity of the generated materials are rigorously assessed. Additionally, a hyperparameter selection scheme for generative models in chemical composition space is developed.

Multidisciplinary Analysis and Optimization Method for Conceptually Designing of Electric Flying-Wing Unmanned Aerial Vehicles

Current unmanned aerial vehicles have been designed by applying the traditional approach to aircraft conceptual design which has drawbacks in terms of the individual analysis of each discipline involved in the conception of new aircraft, the reliance on the designer’s experience and intuition, and the inability of evaluating all possible design solutions. Multidisciplinary analysis and optimization focus on solving these problems, by synthesizing all the disciplines involved and accounting for their mutual interaction. This study presents a multidisciplinary analysis and optimization method for conceptually designing electrical flying-wing micro-unmanned aerial vehicles. The conceptual design task was formulated as a non-linear mathematical programming problem. The method considers the trimming of the UAV during each mission profile phase, consisting of the climb, cruise, and descent. We used two algorithms, one for design space exploration and another for optimization. Typical examples of solving conceptual design problems were considered in the work: the modernization of an existing UAV; the effect of the change of the payload and endurance change on the takeoff weight; and the influence of different static margins on aerodynamic characteristics. The advantages of using this design method are the remotion of additional internal cycles to solve the sizing equation at each optimization step, and the possibility of not only obtaining a unique optimal solution but also a vector of optimal solutions.

NDP-RANK: Prediction and ranking of NDP systems performance using machine learning

The near-data processing (NDP) paradigm has recently gained popularity as a promising method for mitigating the memory wall challenges of future computing systems. Modern 3D-stacked DRAM memories can be leveraged to prevent unnecessary data movement between the main memory and the CPU. However, identifying which type of NDP system, in terms of processing elements and the type of high performance 3D memory used, is suitable for a given application is not a trivial task. Understanding the interactions between modern workloads and the memory subsystem requires a lot of effort. Each memory type presents its unique advantages and shortcomings. In addition, memory access patterns vary greatly across applications. Therefore, the performance of a given application on a given memory type is difficult to intuitively predict. There is no specific NDP system or memory type that can provide high performance for every application.We propose NDP-RANK, a machine learning framework that can efficiently decide which NDP system is suitable for an application. NDP-RANK’s performance prediction is based on an input set of application and microarchitecture characteristics. We build machine learning models that can be used to conduct design-space exploration of NDP systems and accurately predict performance of previously unseen applications on several NDP architectures. Our models are orders of magnitude faster than architectural simulation. They can accurately predict performance with coefficients of determination ranging between 0.89 and 0.96, and root mean square errors ranging between 0.04 and 0.16.

Intent-Driven Secure System Design: Methodology and Implementation

Given the typical complexity of networked systems in terms of number of components and their interconnections, manually designing their architecture is inherently difficult, and the design process requires expert knowledge and skills. If we also consider the security requirements that networked systems must meet, the task becomes even more demanding, since the manual audit and security mitigation of the architecture are time and labor intensive. This led to research on automated system design, including ways to cover the related security aspects.In this paper we present a methodology for secure system design that uses an intent-based representation of the network service requirements as input, which is annotated with security requirements, and applies the Design Space Exploration (DSE) approach to generate the system design. Security is handled via a MITRE ATT&CK-based security knowledge base, and a set of security check functions, so that the resulting system design meets not only the functional and quantitative requirements, but also the specified security requirements. We implemented this methodology as the secure system designer SecureWeaver by extending the functionality of an existing intent-based system designer that targeted IT/NW services, named Weaver. A case study of a typical corporate network scenario is used to illustrate the feasibility of the methodology in producing a system design that mitigates the associated security threats. The performance evaluation we conducted for this scenario demonstrates that the added security check overhead does not have a significant impact on the overall performance characteristics of the framework.

HARDeNN: Hardware-assisted attack-resilient deep neural network architectures

We propose HARDeNN, a low-overhead end-to-end inference accelerator methodology to armor the underlying pre-trained neural network architecture against black-box non-input adversarial attacks. In order to find the most vulnerable neural network architectures parameters, a hardware-assisted fault injection tool and a statistical stress model have been proposed to synergy uniform fault assessment across layers and targeted in-layer fault assessment to realize a holistic, rigorous fault evaluation in NN topologies susceptible to non-input adversarial black-box attacks. The key observation from the assessment shows that the weights and activation functions are the most vulnerable neural network parameters that are susceptible to both single-bit and multiple-bit flip attacks. Concerning the aforementioned parameters, a multi-objective design space exploration is conducted to find a superior design under different resource constraints. The error-resiliency magnitude offered by HARDeNN can be adjusted based on the given boundaries. The experimental results show that HARDeNN methodology enhances the error-resiliency magnitude of cnvW1A1 by 17.19% and 96.15% for 100 multi-bit upsets that target weight and activation layers, respectively, during CIFAR-10 classification.© 2017 Elsevier Inc. All rights reserved.

Design Space Exploration of Clustered Sparsely Connected MPSoC Platforms.

Heterogeneous multiprocessor platforms are the foundation of systems that require high computational power combined with low energy consumption, like the IoT and mobile robotics. In this paper, we present five new algorithms for the design space exploration of platforms with elements grouped in clusters with very few connections in between, while these platforms have favorable electric properties and lower production costs, the limited interconnectivity and inability of heterogeneous platform elements to execute all types of tasks, significantly decrease the chance of finding a feasible mapping of application to the platform. We base the new algorithms on the Non-dominated Sorting Genetic Algorithm II (NSGA-II) meta-heuristic and the previously published SDSE mapping algorithm designed for fully interconnected multiprocessor platforms. With the aim to improve the chance of finding feasible solutions for sparsely connected platforms, we have modified the parts of the search process concerning the penalization of infeasible solutions, chromosome decoding, and mapping strategy. Due to the lack of adequate existing benchmarks, we propose our own synthetic benchmark with multiple application and platform models, which we believe can be easily extended and reused by other researchers for further studying this type of platform. The experiments show that four proposed algorithms can find feasible solutions in 100% of test cases for platforms with dedicated clusters. In the case of tile-like platforms, the same four algorithms show an average success rate of 60%, with one algorithm going up to 84%.