Evaluation of gem5 for performance modeling of ARM Cortex-R based embedded SoCs

Abstract

ARM CPUs are prevalent in embedded systems ranging from low-power IoT to reasonably high-powered mobile phones and devices. Embedded SoCs integrate a number of accelerators with CPUs to achieve the tight performance and power budget. To overcome the challenges of architecting these complex SoCs, designers employ performance simulators as a design space exploration tool. Developing such a simulator infrastructure in itself is challenging and depends on accurately modeling the ARM CPUs and the interaction of various accelerators with the CPU. The widely used, open-source gem5 simulator provides the necessary components to develop such an infrastructure in a time and cost-effective manner. In this paper, we present the limit study and evaluation of using gem5 for building a performance modeling and analysis framework targeted to ARM R series CPU-based embedded SoC. First, we illustrate the approach to develop the framework by tuning the extensive configuration space of gem5 and making modifications for new features. We consider different CPUs, branch predictors, memory modules, and SystemC coupling in gem5. Second, we perform a detailed correlation of the simulator with a real ARM CPU and explain the shortcomings, challenges, and ways to improve the accuracy. We obtain average absolute errors of 13% for the Embench suite Bennett et al. (2019). We also point out large miscorrelations for specific pattern in ALU (50%), Branch (135%) and Memory (35%). Finally, through a case study to design a flexible NVMe SSD controller architecture, we demonstrate the framework’s design space exploration capabilities.