Design Of Random Number Generator Research Articles

Guidelines for the Design of Random Telegraph Noise-Based True Random Number Generators

Guidelines for the Design of Random Telegraph Noise-Based True Random Number Generators

Entropy Computation for Oscillator-based Physical Random Number Generators

In this paper, we provide a complete set of algorithms aimed at the design and security evaluation of oscillator-based True Random Number Generators (TRNG). While depending on some TRNG design assumptions, the proposed algorithms use as inputs the statistical parameters of the underlying random physical process such as the clock jitter originating from the thermal noise and give a lower bound of the entropy rate of the generated bit stream as output. We describe the general structure of a TRNG composed of multiple free-running oscillators and samplers, the outputs of which are post-processed by an entropy conditioner. Depending on the specification of the entropy conditioner, which can usually be any Boolean function, we describe several algorithmic optimizations. We then explain how to compute and efficiently manage the entropy rate at the output of such a post-processing block and at the output of the generator as a whole.

Designing hardware for a robust high-speed cryptographic key generator based on multiple chaotic systems and its FPGA implementation for real-time video encryption

Recent advancements in communication technologies have highlighted the pivotal role of information security for all individuals and entities. In response, researchers are increasingly focusing on cryptographic solutions to ensure the reliability of confidential information. Recognizing the superiority of chaotic systems preference as entropy source of cryptographic systems, this paper proposes a novel true random number generator (TRNG) design by combining four different chaotic systems outputs, tailored for real-time video encryption application. These chaotic systems are continuous-time Lorenz and fractional-order Chen-Lee systems, as well as discrete-time Logistic and Tent maps. This study generates true random bit (TRB) sequences at a high bit rate (25 Mbps) through the hardware implementations of four distinct chaotic systems to have the best statistical randomness in the resulting output. Then, the cryptographic true random key bits (8-bit at 25 MHz frequency) are employed in the post-processing with real-time video data by using the XOR operation, a fundamental post-processing algorithm. The real-time video encryption application is executed on an experimental assembly, composed of a Field Programmable Gate Array (FPGA) development kit, an OV7670 camera module, a VGA monitor, and prototype circuit boards for the chaotic systems. To evaluate the effectiveness of the proposed encryption system, several security assessments are conducted. These include NIST SP 800 − 22 statistical tests, FIPS 140-1 standards, chi-square tests, histogram and correlation analysis, and NPCR and UACI differential attack resilience tests. Consequently, the findings suggest that the presented real-time embedded cryptosystem is robust and suitable for secure communications, particularly in the realm of video transmission.

Incommensurate fractional-order analysis of a chaotic system based on interaction between dark matter and dark energy with engineering applications

Chaotic systems, characterized by their sensitivity to initial conditions and the presence of deterministic unpredictability, have garnered significant attention in various fields of science and engineering. Researchers have demonstrated a growing interest in recent years in identifying various physical systems as chaotic system, including but not limited to fluid dynamics, electrical circuits, and biological oscillators. In this study, a cosmological chaotic system that portrays the interaction between dark matter and dark energy is examined using incommensurate fractional-order analysis. The effects of incommensurate fractional orders are evaluated by means of phase portraits, bifurcation diagrams and Lyapunov exponents spectra. It is dedicated that wider chaotic regions are observed once the values of these incommensurate fractional orders are changed. Meanwhile, a hidden attractor is found based on the stability analysis and basin of attraction in the incommensurate fractional-order dark matter and dark energy (IFODMDE) chaotic system. These findings highlight the richer dynamic characteristics of the IFODMDE chaotic system. Furthermore, the identified hidden attractor is effectively employed in this study for various engineering applications, including chaos control, random number generator (RNG) design, and image encryption. The analytical results offer a more accurate description of real-world physical phenomena, thanks to the inclusion of incommensurate fractional orders. The application results prove the good randomness of the IFODMDE chaotic system.

A Novel Design of Random Number Generators Using Chaos-Based Extremum Coding

A Novel Design of Random Number Generators Using Chaos-Based Extremum Coding

Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness

Design of True Random Number Generator Based on Multi-Ring Convergence Oscillator Using Short Pulse Enhanced Randomness

Self-Parameterized Chaotic Map for Low-Cost Robust Chaos

This paper presents a general method, called “self-parameterization”, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide robust performance by enlarging the design space in many hardware-security applications, including reconfigurable logic and encryption. The proposed self-parameterization scheme uses only one existing chaotic map, referred to as the seed map, and a simple transformation block. The effective control parameter of the seed map is treated as an intermediate variable derived from the input and control parameter of the self-parameterized map, under some constraints, to achieve the desired functionality. The widening of the chaotic region after adding self-parameterization is first demonstrated on three ideal map functions: Logistic; Tent; and Sine. A digitized version of the scheme was developed and realized in a field-programmable gate array (FPGA) implementation. An analog version of the proposed scheme was developed with very low transistor-count analog topologies for hardware-constrained integrated circuit (IC) implementation. The chaotic performance of both digital and analog implementations was evaluated with bifurcation plots and four established chaotic entropy metrics: the Lyapunov Exponent; the Correlation Coefficient; the Correlation Dimension; and Approximate Entropy. An application of the proposed scheme was demonstrated in a random number generator design, and the statistical randomness of the generated sequence was verified with the NIST test.

Jitter-based Adaptive True Random Number Generation Circuits for FPGAs in the Cloud

In this article, we present and evaluate a true random number generator (TRNG) design that is compatible with the restrictions imposed by cloud-based Field Programmable Gate Array (FPGA) providers such as Amazon Web Services (AWS) EC2 F1. Because cloud FPGA providers disallow the ring oscillator circuits that conventionally generate TRNG entropy, our design is oscillator-free and uses clock jitter as its entropy source. The clock jitter is harvested with a time-to-digital converter (TDC) and a controllable delay line that is continuously tuned to compensate for process, voltage, and temperature variations. After describing the design, we present and validate a stochastic model that conservatively quantifies its worst-case entropy. We deploy and model the design in the cloud on 60 EC2 F1 FPGA instances to ensure sufficient randomness is captured. TRNG entropy is further validated using NIST test suites, and experiments are performed to understand how the TRNG responds to on-die power attacks that disturb the FPGA supply voltage in the vicinity of the TRNG. After introducing and validating our basic TRNG design, we introduce and validate a new variant that uses four instances of a linkable sampling module to increase the entropy per sample and improve throughput. The new variant improves throughput by 250% at a modest 17% increase in CLB count.

A dynamically reconfigurable entropy source circuit for high-throughput true random number generator

—True random number generator is an important hardware security primitive. Entropy source is the key to the design of a high-throughput true random number generator. To improve the throughput of a true random number generator while maintaining low hardware overhead, a novel entropy source circuit using ring oscillator with dynamically reconfigurable delay chain is proposed in this paper. The proposed entropy source exploits both signal jitter and circuit metastability. It consists of a seventh-order cycle shift register, seven 2-1MUXs and a core loop delay chain that is composed of inverters in series. Under the control of a high-frequency clock, the cycle shift register generates state transitions to control the output of MUXs, which in turn changes the number of inverters connected in the delay chain, switching the operation of the ring between steady and oscillating states. The outputs of five entropy sources are sampled and further XOR-ed with D flip-flops at a sampling clock of 400 MHz to obtain true random numbers. The proposed TRNG is implemented on the Xilinx Virtex-6 FPGA. The random numbers are captured in real-time using the Xilinx ChipScope and the TRNG is tested using the standard test specifications. The experimental results show that when working under a throughput of 400 Mbps, the proposed TRNG passes the NIST SP800-22 and the NIST SP800–90 B tests with a passing rate greater than 98% and a minimum entropy index per bit greater than 0.99. It also passes the relevant performance tests including autocorrelation test, restart test, deviation test, and temperature and voltage fluctuation test, and it has low hardware overhead.

Design and implementation of a robust random number generator based on chaotic ring oscillators

In this paper, the design and implementation of a robust random number generator (RNG) based on chaotic ring oscillators is presented. The RNG output bits are generated through the chaotic sampling of chaotic waveform (CSCW) where the chaotic signals are obtained from two separate nodes of a chaotic ring oscillator (CRO). The proposed RNG is implemented on a FPGA (field-programmable gate array) combined with lumped elements on a breadboard circuit. The output bitstream of the proposed RNG passed the NIST 800-22 statistical randomness test suite without any need for post processing. To analyze the robustness of the CSCW method, a comparative analysis is conducted between chaos-based bit generation methods in terms of robustness against external interference. It is demonstrated that the proposed CSCW method ensures higher immunity of the RNG against external interference.

A Novel Random Number Generator and Its Application in Sound Encryption Based on a Fractional-Order Chaotic System

Random number generator design is one of the practical applications of nonlinear systems. This study used random number generation and sound encryption application with a fractional chaotic system. Random numbers were generated with the Langford chaotic system, and a sound encryption application was carried out for the secure transmission of voice messages. Randomization performance of numbers was evaluated by employing NIST-800-22 statistical tests, which meet the highest international requirements. It was observed that the distributions of these generated random numbers reached the desired level of randomness after the examination. Unlike the integer-order random number generators widely used in the literature, the fractional-order Langford chaotic system was employed to generate and analyze random numbers and demonstrate their utilization in sound encryption. Random numbers generated from a fractional degree-based chaotic system developed in this study can be used in cryptology, secret writing, stamping, statistical sampling, computer simulations, dynamic information compression and coding.

Quantum Randomness in Cryptography—A Survey of Cryptosystems, RNG-Based Ciphers, and QRNGs

Cryptography is the study and practice of secure communication with digital data and focuses on confidentiality, integrity, and authentication. Random number generators (RNGs) generate random numbers to enhance security. Even though the cryptographic algorithms are public and their strength depends on the keys, cryptoanalysis of encrypted ciphers can significantly contribute to the unveiling of the cipher’s key. Therefore, to ensure high data security over a network, researchers need to improve the randomness of keys as they develop cryptosystems. Quantum particles have a leading edge in advancing RNG technology as they can provide true randomness, unlike pseudo-random numbers generators (PRNGs). In order to increase the level of the security of cryptographic systems based on random numbers, this survey focuses on three objectives: Cryptosystems with related cryptographic attacks, RNG-based cryptosystems, and the design of quantum random number generators (QRNGs). This survey aims to provide researchers with information about the importance of RNG-based ciphers and various research techniques for QRNGs that can incorporate quantum-based true randomness in cryptosystems.

Hybrid Design of Pseudo Random Number Generator Using Shift Register FPGA and CMOS VLSI

The proliferation of digital systems in various applications necessitates the development of efficient pseudo-random number generators (PRNGs) for cryptographic and data processing purposes. In this study, we present a novel approach to PRNG design, leveraging a hybrid combination of Shift Register Field-Programmable Gate Arrays (FPGA) and Complementary Metal-Oxide-Semiconductor (CMOS) Very Large-Scale Integration (VLSI) technology. This hybrid design capitalizes on the strengths of both FPGA and CMOS VLSI to achieve enhanced performance and versatility. The FPGA-based component of the PRNG system offers configurability and parallelism, allowing for rapid and customizable PRNG generation. The CMOS VLSI component, on the other hand, ensures low power consumption and compact integration, ideal for embedded applications. By combining these two technologies, the PRNG achieves a delicate balance between flexibility and efficiency. We evaluate the hybrid PRNG design through rigorous testing and analysis, including statistical tests, spectral tests, and computational performance assessments. Our results demonstrate that the hybrid PRNG outperforms standalone FPGA or CMOS-based PRNGs in terms of randomness, uniformity, and speed, making it suitable for a wide range of applications in cryptography, secure communications, and data processing. The hybrid PRNG design presented in this study not only contributes to the advancement of PRNG technology but also offers a versatile solution for engineers and researchers seeking to tailor their PRNG systems to specific application requirements while optimizing performance and energy efficiency.

FPGA implantations of TRNG architecture using ADPLL based on FIR filter as a loop filter

This article describes about the design, implementation, and analysis of a true random number generator (TRNG) employing an all-digital phase-locked loop (ADPLL) based on a finite impulse response (FIR) filter as the digital loop filter and implemented on the Artix 7(XC7A35T-CPG236-1) field programmable gate array (FPGA) board using the Xilinx Vivado v.2015.2 design suite. The coefficients of a 3rd-order broadcast low-pass digital FIR filter are computed using the Keiser window method. The MATLAB-FDA tool is used to calculate the filter coefficient. After reducing the bias in the sequence using the XOR-corrector post-processing approach, the suggested ADPLL-based TRNG designs created an unbiased stochastic random number with an overall throughput of 200 Mbps for both designs. The first proposed FIR-ADPLL-based TRNG design (FAT-1) consumes 0.072 W of power, whereas the second proposed FIR-ADPLL-based TRNG design (FAT-2) consumes 0.074 W. The resulting bitstream is verified for randomness using national institute of standards and technology (NIST) test following post-processing. Digital storage oscilloscope (DSO) is interfaced to the Artrix-7 FPGA board in order to capture the TRNG output waveforms. Both the proposed FIR-based ADPLL-TRNG designs passed the NIST SP 800-22 test, indicating that they are well-suited for a variety of industrial applications, including network security, cybersecurity, banking security, smart cards, radio-frequency identification tags, Internet of Things, and Industrial Internet of Things.

Cascading CMOS-Based Chaotic Maps for Improved Performance and Its Application in Efficient RNG Design

We present a general framework for improving the chaotic properties of CMOS-based chaotic maps by cascading multiple maps in series. Along with two novel chaotic map topologies, we present the 45 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$nm$ </tex-math></inline-formula> designs for four CMOS-based discrete-time chaotic map topologies. With the help of the bifurcation plot and three established entropy measures, namely, Lyapunov exponent, Kolmogorov entropy, and correlation coefficient, we present an extensive chaotic performance analysis on eight unique map circuits (two under each topology) to show that under certain constraints, the cascading scheme can significantly elevate the chaotic performance. The improved chaotic entropy benefits many security applications and is demonstrated using a novel random number generator (RNG) design. Unlike conventional mathematical chaotic map-based digital pseudo-random number generators (PRNG), this proposed design is not completely deterministic due to the high susceptibility of the core analog circuit to inevitable noise that renders this design closer to a true random number generator (TRNG). By leveraging the improved chaotic performance of the transistor-level cascaded maps, significantly low area and power overhead are achieved in the RNG design. The cryptographic applicability of the RNG is verified as the generated random sequences pass four standard statistical tests namely, NIST, FIPS, Diehard, and TestU01.

Design of Hybrid True Random Number Generator for Cryptographic Applications

In real-time applications, unpredictable random numbers play a major role in providing cryptographic and encryption processes. Most of the existing random number generators are embedded with the complex nature of an amplifier, ring oscillators, or comparators. Hence, this research focused more on implementing a Hybrid Nature of a New Random Number Generator. The key objective of the proposed methodology relies on the utilization of True random number generators. The randomness is unpredictable. The additions of programmable delay lines will reduce the processing time and maintain the quality of randomizing. The performance comparisons are carried out with power, delay, and lookup table. The proposed architecture was executed and verified using Xilinx. The Hybrid TRNG is evaluated under simulation and the obtained results outperform the results of the conventional random generators based on Slices, area and Lookup Tables. The experimental observations show that the proposed Hybrid True Random Number Generator (HTRNG) offers high operating speed and low power consumption.

Design and Synchronization of Chaos-Based True Random Number Generators and Its FPGA Implementation

In this paper, a new chaos-based true random number generator (TRNG) and a sliding mode controller (SMC) to synchronize the proposed TRNGs are proposed. Firstly, the continuous chaotic system is transformed into a discrete system that preserves the original continuous system’s chaotic behavior and makes it easy to realize with the field-programmable gate array (FPGA) for synchronization control. Then, a discrete SMC is introduced to solve the synchronization problem of the master-slave discrete chaotic systems. Subsequently, a novel hybrid function integrated with the El-Gamal algorithm is proposed to complete the TRNG design. Finally, the FPGA-based realization of the synchronized master-slave TRNGs is implemented. The randomness quality of the proposed TRNGs has been ensured by using Shannon’s entropy and histogram analysis. Furthermore, the National Institute of Standards and Technology (NIST) test suite has also been introduced to evaluate the proposed TRNGs and compare with the existing results in the literature.

A 2D Chaotic Oscillator for Analog IC

In this paper, we have proposed the design of an analog two-dimensional (2D) discrete-time chaotic oscillator. 2D chaotic systems are studied because of their more complex chaotic behavior compared to one-dimensional (1D) chaotic systems. The already published works on 2D chaotic systems are mainly focused either on the complex analytical combinations of familiar 1D chaotic maps such as Sine map, Logistic map, Tent map, and so on, or off-the-shelf component-based analog circuits. Due to complex hardware requirements, neither of them is feasible for hardware-efficient integrated circuit (IC) implementations. To the best of our knowledge, this proposed work is the first-ever report of an analog 2D discrete-time chaotic oscillator design that is suitable for hardware-constrained IC implementations. The chaotic performance of the proposed design is analyzed with bifurcation plots, the transient response, 2D Lyapunov exponent, and correlation coefficient measurements. It is demonstrated that the proposed design exhibits promising chaotic behavior with low hardware cost. The real-world application of the proposed 2D chaotic oscillator is presented in a random number generator (RNG) design. The applicability of the RNG in cryptography is verified by passing the generated random sequence through four standard statistical tests namely, NIST, FIPS, TestU01, and Diehard.

Design of True Random Number Generator Using Fingerprint as an Entropy Source and Its Implementation in S-Box

This paper deals with the design of a true random number generator (TRNG) using the fingerprint as an entropy source and its implementation in substitution box (S-box) of Advanced Encryption Standard (AES). Considering fingerprint as a unique and random arrangement of minutiae, these minutiae points are used as the source of entropy. The proposed design utilizes fewer resources minimizing hardware redundancy and enhancing the level of randomness. This TRNG has been designed and validated using Artix-7 FPGA. The data rate, speed and latency have been obtained as 40 Mbps, 5 Mbps and 305 ns, respectively. The generated random bit stream had also been sampled and converted to a binary format in MATLAB and tested through the National Institute of Standards and Technology (NIST) 800.22 statistical suite for validation. The proposed TRNG design pass efficiency achieved is more than 95% for a sample size of 10 binary sequences.

Design and implementation of true random number generators based on semiconductor superlattice chaos

True random number generator (TRNG) is of the fundamental guarantees of information security. However, the commercially-available all-electronic TRNGs, no matter whether the thermal-noise-based or the oscillator-based ones, can merely reach the speed of a few Mbit/s due to the very limited entropy source, which is unable to meet the requirements of ultra-high-speed and ultra-large capacity of information propagation or storage. This paper proposes the design and implementation of semiconductor superlattice random number generator (SSL-RNG) by employing semiconductor superlattice chaos as entropy source. We introduce the entropy estimation method to evaluate the raw data from the entropy harvester quantitatively, thus optimized the parameter design of the LFSR-Toeplitz extractor for post-processing. We have also integrated the entropy acquisition circuit into an embedded FPGA-based platform as a standalone design to trade off the performance and cost. The resulting hardware's output passes the NIST standard statistical test with a full entropy throughput above 300 Mbit/s.