Design and implementation of a robust random number generator based on chaotic ring oscillators

Abstract

In this paper, the design and implementation of a robust random number generator (RNG) based on chaotic ring oscillators is presented. The RNG output bits are generated through the chaotic sampling of chaotic waveform (CSCW) where the chaotic signals are obtained from two separate nodes of a chaotic ring oscillator (CRO). The proposed RNG is implemented on a FPGA (field-programmable gate array) combined with lumped elements on a breadboard circuit. The output bitstream of the proposed RNG passed the NIST 800-22 statistical randomness test suite without any need for post processing. To analyze the robustness of the CSCW method, a comparative analysis is conducted between chaos-based bit generation methods in terms of robustness against external interference. It is demonstrated that the proposed CSCW method ensures higher immunity of the RNG against external interference.