Design Of Random Number Generator Research Articles

Mixture Density Networks-Based Knock Simulator

This paper proposes a statistical simulator for the engine knock based on the Mixture Density Network (MDN) and the accept-reject method. The proposed simulator can generate the random knock intensity signal corresponding to the input signal. The generated knock intensity has a consistent probability distribution with the real engine. Firstly, the statistical analysis is conducted with the experimental data. From the analysis results, some important assumptions on the statistical properties of the knock intensity are made. Regarding the knock intensity as a random variable on the discrete-time index, it is independent and identically distributed if the input of the engine is identical. The probability distribution of the knock intensity under identical input can be approximated by the Gaussian Mixture Model(GMM). The parameter of the GMM is a function of the input. Based on these assumptions, two sub-problems for establishing the statistical simulator are formulated: One is to approximate the function from input to the parameters of the knock intensity distribution with an absolutely continuous function; The other one is to design a random number generator that outputs the random data consistent with the given distribution. The MDN is applied to approximate the probability density of the knock intensity and the accept-reject algorithm is used for the random number generator design. The proposed method is evaluated in experimental data-based validation.

TRNGs from Pre-Formed ReRAM Arrays

Schemes generating cryptographic keys from arrays of pre-formed Resistive Random Access (ReRAM) cells, called memristors, can also be used for the design of fast true random number generators (TRNG’s) of exceptional quality, while consuming low levels of electric power. Natural randomness is formed in the large stochastic cell-to-cell variations in resistance values at low injected currents in the pre-formed range. The proposed TRNG scheme can be designed with three interconnected blocks: (i) a pseudo-random number generator that acts as an extended output function to generate a stream of addresses pointing randomly at the array of ReRAM cells; (ii) a method to read the resistance values of these cells with a low injected current, and to convert the values into a stream of random bits; and, if needed, (iii) a method to further enhance the randomness of this stream such as mathematical, Boolean, and cryptographic algorithms. The natural stochastic properties of the ReRAM cells in the pre-forming range, at low currents, have been analyzed and demonstrated by measuring a statistically significant number of cells. Various implementations of the TRNGs with ReRAM arrays are presented in this paper.

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

This study presents a novel Dormand-Prince-based hybrid chaotic True Random Number Generator Design (TRNG) that can be used for secure communication and cryptographic applications on Field Programmable Gate Array (FPGA). In this design, a chaotic oscillator unit has been implemented with an FPGA-based Sprott-Jafari chaotic oscillator model suitable with IQ-Math fixed point number and IEEE 754-1985 floating point number standards. Random numbers have been produced with the quantization of the results generated by the chaotic oscillator. XOR has been performed with FPGA-based ring oscillator structure on the post-processing unit so as to enhance the randomness. The differential equation of the chaotic system used in the TRNG design was modelled using Dormand-Prince numerical algorithm method. The design on FPGA has been realized in two separate number formats including 32-bit (16I-16Q) IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard. The realized designs have been coded in VHDL, a hardware description language, and the Xilinx ISE 14.7 program has been used for the system design. Two separate TRNG designs have been synthesized and tested for the Virtex-6 (XC6VLX240T-1FF1156) FPGA chip. The maximum operating frequency of the TRNG with 32-bit IQ-Math fixed point number standard is 344.585 MHz and the throughput is approximately 344 Mbit/s. The maximum operating frequency of the TRNG with 32-bit IEEE 754-1985 floating point number standard is 316.756 MHz and the throughput is 316 Mbit/s. 1 Mbit sequence has been generated by both designed TRNG systems. Randomness analysis of the generated numbers has been performed in accordance with the NIST 800-22 tests and the generated numbers have successfully passed all of the tests.

Design, FPGA-based Implementation and Performance of a Pseudo Random Number Generator of Chaotic Sequences

Pseudo-Random Number Generator of Chaotic Sequences (PRNG-CS) has caught the attention in various security applications, especially for stream and block ciphering, steganography, and d ...

A 0.7 pJ/bit, 1.5 Gbps Energy-Efficient Image-Based True Random Number Generator

ABSTRACT Random numbers cover a vast spectrum of applications. Hence generating it effectively with high performance is the need of the hour. This paper presents the novel design and implementation of high performance and energy-efficient true random number generator (TRNG) using images as a source. In the proposed work, the harvesting mechanism that comprises of hashing technique block (HTB) is used to reduce the intensity of pattern, an event counting circuit (ECC) is used for comparing the events, while a linear feedback shift register (LFSR), designed by considering a primitive polynomial function, is used to obtain the random numbers. The addition of 8 × 1 multiplexer (MUX) with meta-stable circuit feeder control lines had further increased the unpredictability in the proposed system. The implementation of the work has been done in the Xilinx Vivado simulation tool followed by the Cadence Virtuoso circuit simulation environment. The maximum speed of 1.5 Gbps with power dissipation of 1 mW and 0.7 pJ/bit energy efficiency with a layout area of 2218 μm2 has been achieved in this work. NIST 800.22 statistical test suite and uniformity test comprising of Kolmogorov–Smirnov and Chi-square test have also been performed for validation of generated random numbers. The obtained binary sequences have passed all tests successfully with calculated entropy up to 0.999999999. The autocorrelation factor (ACF) of the output bit streams has been obtained as approximately zero (∼0) within 96% confidence bounds of a Gaussian distribution (µ = 0, 3σ). The proposed design is thus suitable for true random number generation.

A Simple Chaotic Flow with Hyperbolic Sinusoidal Function and Its Application to Voice Encryption

In this article, a new chaotic system with hyperbolic sinusoidal function is introduced. This chaotic system provides a new category of chaotic flows which gives better perception of chaotic attractors. In the proposed chaotic flow with hyperbolic sinusoidal function, according to the changes of parameters of the system, the self-excited attractor and two forms of hidden attractors are occurred. Dynamic behavior of the offered chaotic flow is studied through eigenvalues, bifurcation diagrams, phase portraits, and spectrum of Lyapunov exponents. Moreover, the existence of double-scroll attractors in real word is considered via the Orcard-PSpice software through an electronic execution of the new chaotic flow and illustrative results between the numerical simulation and Orcard-PSpice outcomes are obtained. Lastly, random number generator (RNG) design is completed with the new chaos. Using the new RNG design, a novel voice encryption algorithm is suggested and voice encryption use and encryption analysis are performed.

High-Throughput Portable True Random Number Generator Based on Jitter-Latch Structure

Under the requirement of highly reliable encryption, the design of true random number generators (TRNGs) based on field-programmable gate arrays (FPGAs) is receiving increased attention. Although TRNGs based on ring oscillators (ROs) and phase-locked loops (PLLs) have the advantages of small resource overhead and high throughput, there are problems such as instability of randomness and poor portability. To improve the randomness, portability, and throughput of a random number generator, we design a TRNG whose randomness is generated by the oscillation of self-timed rings (STRs) and accurately extracted by a jitter-latch structure. The portability of the structure is verified by electronic design automation (EDA) tools. Under the condition of 0°C-80°C ambient temperature and 1.0 ± 0.1 V output voltage, the proposed structure is tested many times on Xilinx Spartan-6 and Virtex-6 FPGAs with an automatic routing mode. Theoretical analysis shows that this method can effectively improve the coverage of jitter and reduce the migration phenomenon. Experimental results show excellent performance in randomness, robustness, and portability, and the throughput reaches 100 Mbps.

0.4 mW, 0.27 pJ/bit true random number generator using jitter, metastability and current starved topology

This study introduces the design of true random number generator (TRNG) using jitter, metastability and current starved topology. The proposed design consisted of a current starved inverter-based ring oscillator (RO) with a high-frequency divider block (designed by T-FF followed by D-FF to address setup and hold time issues), jitter extraction and metastable block followed by two sampling blocks. The design avails fewer amenities to yield the reduction in hardware and enhances the degree of randomness. The post-layout simulation of the proposed work was performed using a 180 nm CMOS technology environment in the Cadence Virtuoso tool. The speed and power dissipation achieved are 1.5 Gbps and 0.4 mW, respectively, with an efficiency of 0.27 pJ/bit. The effect of temperature and variation in supply voltages (by 10% around its nominal value) is also investigated on the generated random numbers through parametric analysis. For validation of randomness, the generated random signals are first sampled and then converted in binary format using MATLAB and finally verified by Kolmogorov–Smirnov and Chi-square test for the uniformity and independency. The validity of the proposed work is done by NIST 800.22 statistical test suite. The proposed TRNG design achieved a very high-pass efficiency.

A novel secure chaos-based pseudo random number generator based on ANN-based chaotic and ring oscillator: design and its FPGA implementation

This paper presents a novel, real time, high speed and robust chaos-based pseudo random number generator (PRNG) design using the structures of artificial neural network (ANN)-based 2D chaotic oscillator and ring oscillator. In this study, four different robust PRNGs have been implemented using four different approaches (TS-55, Elliott-93, Elliott-2, Cordic-LUT) of TanSig activation functions (TSAF) that have been used in the design of ANN-based 2D chaotic oscillators. The designs have been coded in VHDL using IEEE-754–1985 number standard. The PRNGs have been synthesized for Virtex-6 FPGA chip using Xilinx ISE Design Tools. After Place&Route operation, FPGA chip statistics and maximum operating frequencies have been presented. The maximum operating frequencies of the proposed PRNGs range between 184 and 241 MHz. The 1 Mbit of bit streams generated by PRNGs have been subjected to NIST-800–22 randomness tests. Among 4 different proposed PRNGs, the proposed PRNGs that designed using the Elliott-93 and Cordic-LUT approaches have successfully passed all NIST-800–22 tests and have a bit production rate of 241 Mbps. The proposed secure hybrid chaos-based PRNG structures were compared with similar studies conducted in the literature in recent years. According to the results, the proposed FPGA-based secure new chaotic PRNG structures are useful in cryptographic applications.

Dynamical analysis, FPGA implementation and its application to chaos based random number generator of a fractal Josephson junction with unharmonic current-phase relation

The dynamical characteristics and its applications to random number generator of a fractal Josephson junction with unharmonic current-phase relation (FJJUCPR) described by a linear resistive-capacitive-inductance shunted junction (LRCLSJ) model are investigated in this paper. The dependence of the equilibrium points of the system to the external current source or the unharmonic current-phase relation (UCPR) parameter is revealed and their stability are analysed. The inclusion of unharmonic current-phase relation in an ideal or a fractal Josephson junction leads to transform the spiking, bursting and relaxations oscillations to an excitable mode. While the inclusion of fractal characteristics in insulating layer of Josephson junction leads to an increase of the amplitude of the spiking, bursting and relaxations oscillations. The numerical simulations results also indicate that FJJUCPR exhibits self-excited chaotic attractors and two different shapes of hidden chaotic attractors. The FJJUCPR is implemented in field programmable gate arrays (FPGA) in order to validate the numerical simulations results. In addition, random number generator design is performed using chaotic signals of the FJJUCPR. The random number generator design results are successful in the NIST SP 800-22 test.

Performance of Memristor Based Ring Oscillators True Random Number Generator for Energy Technology

We are living in an era where everything is trying to be more connected in terms of the different physical entities and its surrounding environment. This new concept that is developing called the Internet of Things (IoT) has garnered a lot of attention [Bodei, 2019 #45]. There are various of applications and smart objects associates with the IoT and this leads to an increase in security challenges. IoT security is very important but getting harder to achieve. One example of utilization of IoT is in the smart grid infrastructure and this in turn increases the need for network security. An integrated internet-based smart grid and energy resources also called Energy Internet (EI) has a lot of security challenges that comes with the current smart grid. Smart grid infrastructure and any means of energy that implements the internet system also known as Energy Internet (EI) has many security challenges that come with the current smart grid. A memristor based ring oscillator True Random Number Generator design has been proposed in this research as a solution that can combat security challenges that existed in the hardware implementation of devices. Inputs based on non-deterministic methods are being used in TRNGs to generate outputs that possessed randomness characteristics in applications of IoT that makes it secure. Complementary metal oxide semiconductor (CMOS) technology of 0.18 μm are being used in the TRNG design and a software of LT SPICE IV helps to realized it.The proposed TRNG design produced output that passed 10 out of the 15 NIST tests, therefore showed that the TRNG produce a fairly random output.

Improving the Security of Wireless Communications on High-Speed Trains by Efficient Authentication in SCN-R

Recently, we have witnessed the remarkable development in high-speed railways around the world. To provide a robust and fast wireless network for the onboard passengers, we have earlier proposed smart collaborative networking for railways (SCN-R). In the realization of SCN-R, its security is challenged by potential exploitation of authentication vulnerabilities since traditional authentication mechanisms are unsuitable for scenarios with fast moving objects due to their complex and relatively timely operations. In this paper, we address this issue by proposing a new efficient authentication mechanism, which is based on a new design of chaotic random number generator (RNG). Comparing with the recent proposal relying on the precise boundaries of chaotic map state spaces, our RNG uses two logistic maps to avoid the time-consuming boundary location process. The proposed authentication mechanism uses the RNG to generate and validate the one-time password (OTP). To support different authentication applications, different lengths of OTPs can be used to differentiate and identify the applications. We have implemented our proposed authentication mechanism under real-world conditions, with results showing the feasibility and effectiveness of our authentication mechanism.

A novel memristive true random number generator design

PurposeIn this work, a true random number generator is designed by sampling the double-scroll analog continuous-time chaotic circuit signals.MethodologyA Chua circuit based on memristance simulator is designed to obtain a non-linear term for a chaotic dynamic system. It is implemented on the board by using commercially available integrated circuits and passive elements. A low precision ADC which is commonly found in the market is used to sample the chaotic signals. The mathematical analysis of the chaotic circuit is verified by experimental results.OriginalityIt is aimed to be one of the pioneering studies (including low precision ADC) in the literature on the implementation of memristive chaotic random number generators.FindingsTwo new methods are proposed for post-processing and creating random bit array using XOR operator and J-K flip flop. The bit stream obtained by a full-hardware implementation successfully passed the NIST-800-22 test. In this respect, the availability of the memristance simulator circuit, memristive chaotic double-scroll attractor, proposed random bit algorithm and the randomness of the memristive analog continuous-time chaotic true number generator were also verified.

Design and Analysis of a True Random Number Generator Based on GSR Signals for Body Sensor Networks.

Today, medical equipment or general-purpose devices such as smart-watches or smart-textiles can acquire a person’s vital signs. Regardless of the type of device and its purpose, they are all equipped with one or more sensors and often have wireless connectivity. Due to the transmission of sensitive data through the insecure radio channel and the need to ensure exclusive access to authorised entities, security mechanisms and cryptographic primitives must be incorporated onboard these devices. Random number generators are one such necessary cryptographic primitive. Motivated by this, we propose a True Random Number Generator (TRNG) that makes use of the GSR signal measured by a sensor on the body. After an exhaustive analysis of both the entropy source and the randomness of the output, we can conclude that the output generated by the proposed TRNG behaves as that produced by a random variable. Besides, and in comparison with the previous proposals, the performance offered is much higher than that of the earlier works.

A true random number generator architecture based on a reduced number of FPGA primitives

This paper reports on the design, realization and characterization of a True Random Number Generator (TRNG) that operates using as seeds of entropy, the jitter and the metastability introduced by primitives of a Field Programmable Gate Arrays (FPGA) board. In particular, the TRNG architecture has been implemented on a Xilinx Ultrascale XCKU040 FPGA board. Generally, the implementations on FPGA of fully-digital TRNGs make use of ring oscillators employing a large number of Look-Up-Table (LUT) blocks. Differently from this approach, this paper demonstrates that a reliable FPGA-based TRNG architecture can be realized mainly employing only a single PLL and three on-board primitives together with other few basic logic elements (i.e., 8 D-type Flip-Flop, 17 LUT and 2 Counters) used only for the initial overall system synchronization and post-processing operations. In this way, the proposed solution largely reduces the employed number of the FPGA Configurable Logic Blocks (CLB), the circuitry complexity and the overall power consumption without affecting the achievable output bit rate so resulting suitable for full-custom VLSI implementations. The random and statistical properties of the generated 100 Mbps output bitstreams have been validated by passing all the National Institute of Standards and Technology (NIST) tests as well as the Anderson-Darling and the Kolmogorov-Smirnov tests so demonstrating that the proposed TRNG architecture can be suitably employed in security/cybersecurity network systems as well as, once integrated, in Internet-of-Things (IoT) and Industrial-Internet-of-Things (IIoT) applications.

Sharing Resources Can Lead to Monostability in a Network of Bistable Toggle Switches

The vision of synthetic biology is to engineer complex cellular systems in a modular fashion. Unfortunately, multiple factors hinder such modular design, thus the scalability of rationally engineering synthetic gene circuits. One major barrier emerges due to the limited availability of shared cellular resources, intertwining the behavior of otherwise disconnected components. It was recently demonstrated that these unwanted and pervasive coupling effects can be accurately predicted both in vitro and in vivo . Here, we not only analyze how these effects influence the collective behavior of multiple toggle switches but we also illustrate how to leverage this predominantly disadvantageous coupling. In particular, we prove that by turning on/off a load module, the network of toggle switches can be switched between monostable and multistable modes. Importantly, this can be achieved without any direct regulatory connection among the toggle switches or between the load module and any of the toggle switches, thus presenting a major experimental advantage over relying on traditional regulatory linkages. This idea of exploiting and leveraging resource competition is illustrated through the design of a cellular random number generator.

Modern random number generator design – Case study on a secured PLL-based TRNG

Abstract Random number generators (RNGs) are basic cryptographic primitives. They are used to generate cryptographic keys, initialization vectors, challenges and nonces in cryptographic protocols, and random masks in countermeasures against side channel attacks. RNGs designed for cryptography must generate unpredictable random numbers. According to recent security standards, the unpredictability of generated random numbers must be thoroughly evaluated. In this paper, we provide a concrete example – a phase-locked loop based RNG protected by novel dedicated embedded tests, on which we show how stringent security requirements including unpredictability of generated numbers can be met, while respecting the standards.

Towards Self-testing Quantum Random Number Generators in Integrated Design

Truly random numbers are in great demand in various applications. Self-testing quantum random number generators provide a way to verify that random numbers indeed come from quantum effects. Optical quantum random number generators of this type are the most promising but due to their relative complexity have been realized only as a macroscopic prototype. Miniaturization of such devices opens the way to commercial use. Quantum photonics provides the means to achieve this goal. We discuss general design of self-testing optical quantum random number generator and the ways to implement it as a compact integrated photonic circuit within current technological reach.

CSRO-Based Reconfigurable True Random Number Generator Using RRAM

In this paper, we propose a high-speed (kilohertz–megahertz), reconfigurable current starved ring oscillator (CSRO)-based true random number generator (TRNG) design. The proposed TRNG exploits the intradevice stochastic variations in resistive RAM switching parameters and random telegraph noise (RTN). We demonstrate the effect of RTN on the jitter of CSRO oscillations. We also propose a methodology to reconfigure the TRNG to generate new random numbers. The proposed 10-bit TRNG is validated by NIST test suite for randomness in the data stream. Energy/bit is 22.8 fJ for generation, and the speed of random data generation is 6 MHz. Security vulnerabilities and countermeasures of the proposed TRNG are also investigated.

A new chaotic system with hidden attractor and its engineering applications: analog circuit realization and image encryption

In this article a simple chaotic flow with hidden attractor is proposed. Various dynamics of this new system such as periodic and chaotic oscillations can be achieved by setting bifurcation parameters in a proper value. Nowadays chaos based engineering applications like encryption and hiding data face some significant problems. Chaotic systems with hidden attractors, which our system belongs to them, may unfold some primary steps to solve these problems. As the first step, chaotic behavior of our proposed system has been realised in physical existence by using the Orcard-PSpise software. We have found a proper qualitative likeness between experimental and simulation result. Then, chaos-based random number generator design is carried out using the proposed chaotic system. The numbers obtained from the random number generator are applied to the NIST 800-22 tests, and all of the random numbers are passed through the all tests. A chaos-based encryption algorithm with a random number generator is developed and image encryption application is implemented. Encryption results are compared with the AES algorithm, and performance and security evaluation of the developed encryption algorithm is performed.