Design Of Programmable Logic Arrays Research Articles

Design and Implementation of Programmable Logic Array Using Quantum Dot Cellular Automata

Quantum Dot Cellular Automata (QCA) is an alternative to CMOS technology. The other technologies proposed by researchers are FINFET, CNTs and MTJ to reduce scalability of CMOS devices. Using Quantum Dot Cellular Automata, the low power, extremely dense circuits are designed. QCA cell is the fundamental unit in building logic gates. These cells are powered using specific clock. QCA cells are used to design basic gates and to realize Boolean expressions. QCA Designer tool is used to carry out simulations. The simulation results are same as theoretical results. The complexity and size of circuits are reduced using QCA. The paper includes design of Programmable Logic Array (PLA).

Evaluation of Energy Efficient High Performance Power Gated Programmable Logic Array’s Under 65 nm Process Technology

The Programmable Logic Array (PLA) forms the major building block in the implementation of sequential and combinational functionalities in VLSI based embedded systems. Increased sub threshold leakage current resulting from the scaling down of the microprocessors carrying PLA causes high power dissipation. In order to improve the energy consumption of future electronic products, we propose a power gating method involving sleepy modes at transistor level implemented using 65 nm technology. This paper describes the design and analysis of PLA’s with footer switches for power gating. A comparative analysis has been made between the AND array, OR array and the inverter elements of the proposed PLA’s and the conventional one. Results produced through simulation confirms an optimized power reduction and the transient analysis of the proposed PLA models is proved to be much better than the conventional PLA.

Design of QCA based Programmable Logic Array using decoder

A novel cost effective design of Programmable Logic Array (PLA) is proposed by recursive use of XOR gate, which is used to design 2×4, 3×8 and 4×16 decoders. The 4×16 decoder is coupled with an OR-Array to implement the proposed PLA using Quantum-dot Cellular Automata (QCA). The design is made effective by substantially reducing QCA wire crossing and cell count. A comparative study shows the minimization of cell count and clock-cycle delay of the XOR and Decoders. The PLA is utilized to design an efficient and delay effective 2 bit full adder.

Design of new high-speed and low-energy dynamic PLA

Programmable logic arrays (PLAs) are popular devices in the realisation of circuits as it can implement any Boolean function. This article proposes a dynamic complementary metal oxide semiconductor (CMOS) PLA based on NOR architecture that uses a secondary clock and feedback phenomena for low energy and high speed. Static power reduction is achieved by blocking the static current flow during evaluation period. The proposed design is simulated at 45 nm CMOS technology using CADENCE VLSI design tool. With respect to the latest low-energy and fastest PLA reported in the literature, the proposed design is 69% faster and consumes 73% less energy.

A Reconfigurable PLA Architecture for Nanomagnet Logic

In order to continue the performance and scaling trends that we have come to expect from Moore’s Law, many emergent computational models, devices, and technologies are actively being studied to either replace or augment CMOS technology. Nanomagnet Logic (NML) is one such alternative. NML operates at room temperature, it has the potential for low power consumption, and it is CMOS compatible. In this aricle, we present an NML programmable logic array (PLA) based on a previously proposed reprogrammable quantum-dot cellular automata PLA design. We also discuss the fabrication and simulation validation of the circuit structures unique to the NML PLA, present area, energy, and delay estimates for the NML PLA, compare the area of NML PLAs to other reprogrammable nanotechnologies, and analyze how architectural-level redundancy will affect performance and defect tolerance in NML PLAs. We will use results from this study to shape a concluding discussion about, which architectures appear to be most suitable for NML.

General design principles of totally self-checking code-disjoint inverter-free PLAs

The author presents a general study of the design of totally self-checking (TSC) code-disjoint (CD) programmable logic arrays (PLAs) under a fault model which covers three classes of PLA faults. It is assumed that both inputs and outputs of a PLA are encoded with an unordered code and that PLAs are inverter-free. It is shown that the necessary condition for TSC and CD properties of a PLA is that the input code is closed. Easily verifyable formal conditions for the existence and verification of a TSC/CD PLA that implements a functional or checking circuit are formulated. The paper tackles the open problem (perhaps the most important for practical applications) of designing TSC/CD PLA-based circuits for highly irregular and incomplete unordered codes which are only required to be composed of some closed unordered subcodes. An important property of all new PLA designs is that they are guaranteed to be crosspoint-irredundant with a test set which is easy to generate. The design approach presented can be readily used for non-PLA circuitry as well.

Crosstalk alleviation for dynamic PLAs

The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. However, like all other dynamic circuits, dynamic PLAs have suffered from the crosstalk noise problem. The main reason is that the regularity of the PLA design style causes a product line parallel to the adjacent product lines on the same layer for a long distance so that the crosstalk noise can be significant. Most previous works attempt to prevent the crosstalk noise by adding additional devices or spacing between wires. However, the prevention may degrade performance and increase area/power. In this paper, the authors propose two techniques to alleviate crosstalk noise for dynamic PLAs. The first technique makes use of the fact that depending on the ordering of product lines, some crosstalk does not cause errors in outputs. A proper ordering can greatly reduce the number of product lines affected by crosstalk noise. The authors also observe that the parallel length between two adjacent lines depends on the input and output ordering. For those product lines which can be affected by crosstalk, they attempt to reduce the parallel length by reordering the input and output lines. They have performed experiments on a large set of MCNC benchmark circuits. The results show that after reordering, 86% of product lines become crosstalk immune and need not be considered for crosstalk prevention.

Analysis and design of high-speed and low-power CMOS PLAs

The programmable logic array (PLA) is a basic and important building circuit for VLSI chips. Operating behaviors of several conventional PLAs are analyzed first to find out their speed and power bottlenecks. Then, new circuit design techniques for the CMOS PLA are proposed in the hopes of fulfilling the requirements of high speed and low power at the same time. Finally, high speed is achieved through the combined effect of utilization of a fast pseudofootless dynamic circuit and a reduced interplane clock delay. On the other hand, low power is achieved because the power consumption from the three main sources, i.e., the AND-plane circuits, the interplane buffers, and the OR-plane circuits, can be reduced significantly and simultaneously. The delay time and the power consumption of the critical path of a PLA are taken as the performance evaluation parameters. When the 50/spl times/50/spl times/64 PLAs are designed in a 0.35-/spl mu/m 1P4M CMOS technology, the maximum operating frequency of the proposed PLA is 1.61 times higher than that of the fastest conventional PLA. Furthermore, power reduction can be as high as 18% and 43% when the operating frequencies are set to be 100 MHz and 50 MHz, respectively, as compared to the most power-efficient conventional PLA.

Design of pseudoexhaustive testable PLA with low overhead

The pseudoexhaustive testing (PET) scheme is an economical approach to testing a large embedded programmable logic array (PLA). The authors propose an efficient algorithm named low overhead PET (LOPET) to partition the product lines. By applying this algorithm, both the area overhead and test length are reduced significantly. >

On the design of random pattern testable PLA based on weighted random pattern testing

Programmable Logic Arrays (PLAs) provide a cost effective method to realize combinational logic circuits. PLAs are often not suitable for random pattern testing due to high fao-in of gates. In order to reduce the effective fan-in of gates, previous random pattern testable (RPT) PLA designs focused on partitioning inputs and product lines. In this paper we propose a new random pattern testable design of PLAs which is suitable for built-in selftest. The key idea of the proposed design is to apply weighted random patterns to the PLA under test. The proposed design method was applied to 30 example PLAs. The performance of the RPT PLAs was measured in the size of test set, area overhead, and time overhead, and compared with two other designs in test length and fault coverage. The experimental results show that the proposed design achieve short test length and high fault coverage.

Design of fault-diagnosable and repairable folded PLAs for yield enhancement

A defect-tolerant PLA (programmable logic array) design with a simple column folding technique to enhance the probe yield is presented. The results show that the design requires less die size than a previous design, while still achieving full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults. The design concept is readily extended to other folding techniques. Among the various folding techniques, the trade-offs are the density improvement and regularity, i.e. the density improvement is often paid for as higher irregularity. In fact, the irregularity often results in a higher defect density. It is concluded that a density improvement does not guarantee a higher overall yield.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Absolute minimization of completely specified switching functions

For the automated design of PLAs (programmable logic arrays) with a minimum size, computationally efficient procedures are needed that can minimize functions of a large number of variables. For such minimization procedures, excessively long processing time and an excessively large memory requirement are major problems to overcome. An absolute minimization procedure is presented for standard PLAs with reduced computation time and memory space. The improvement achieved by this procedure, which is based on the decomposition of ratio sets, is mainly due to the detection of all essential prime implicants during the derivation of inclusion functions and to the merger of two procedures previously published by R.B. Cutler and S. Muroga (1987) into one efficient procedure. >

Switch-level testability of the dynamic CMOS PLA

Functional testing, as opposed to parametric testing, plays an important role in testing VLSI integrated circuits. However, it appears that designs are not always carefully analysed in advance to determine precisely which faults are clean, i.e. testable by logic means alone. The programmable logic array (PLA) is a popular circuit form used to implement a system of Boolean functions over a set of input variables. This paper considers the testability of the dynamic CMOS PLA with respect to an extended switch-level fault model that includes node faults, transistor stuck-opens and stuck-ons, interconnect breaks, ohmic shorts, and crosspoint faults. Single occurrences of each fault in the fault model are classified as either clean, unclean, or clean subject to conditions on the products and output functions computed by the PLA. Finally, a modified dynamic CMOS PLA design is described and its improved switch-level testability properties are given.

Design of fault diagnosable and repairable PLA's

Presents a complete fault-tolerant programmable logic array (PLA) design that includes both fault diagnosability and repairability. The proposed PLA design is capable of detecting, locating, and repairing single and multiple stuck-at, bridging, and crosspoint faults. The results of this study show that the total augmented area overhead for both repair and fault diagnosis is nearly 15 to 25 percent over the original PLA, but the chip yield can be improved significantly. >

On the optimal design of multiple-valued PLAs

A description is given of the design and analysis of three types of multivalued PLAs (programmable logic arrays). Type 1 PLAs realize functions directly in the form of the max of min of literal functions and constants. In Type 2 PLAs, the body of the PLA is binary and the output is encoded as a multiple-valued logic value. Type 3 PLAs are the same as type 2 PLAs except for the use of 2-bit decoders and a permutation network on the input. Using the number of columns required to realize a given function as a measure to compare PLAs, it is shown that type 3 PLAs are superior to type 2, which in turn are superior to type 1.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Enhancing random-pattern coverage of programmable logic arrays via masking technique

A testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns is presented. The proposed design is realized with low area overhead by adding two mask arrays to the AND and OR arrays of the PLA. An experiment was performed to demonstrate the effect of the masking technique. In the experiment, eight large PLAs were modified by adding mask arrays of various sizes; fault simulation with random patterns for modified and unmodified PLAs was then carried out to obtain random-pattern test coverage curves. Fault coverage can be significantly enhanced via the proposed masking technique with very low area overhead. >

Analysis of testable PLA designs

A framework is presented for evaluating methods of testing programmable logic arrays (PLAs), and the attributes of 25 test design methodologies are tabulated. PLA testing problems are first examined, and several test-generation algorithms are briefly described. Techniques for designing testable designs are examined, namely, special coding, parity checking, signature analysis, divide and conquer, and fully testable PLAs. The attributes that make a good testable design are then discussed. They fall into four categories: (1) testability characteristics; (2) effect on original design; (3) requirements of the application environment; and (4) design costs, i.e. how difficult it is to implement the technique.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On the design of pseudoexhaustive testable PLAs

A method is presented to design pseudoexhaustive testable (PET) PLAs (programmable logic arrays) that are suitable for BIST (built-in self-test) environments. The key idea of the design is to partition inputs and product lines into groups. During testing, a group of inputs and a group of product lines are selected and tested exhaustively. The proposed design leads to small test sizes and relatively small area overhead. Experimental results on 30 PLAs, comparing test set sizes and area overhead of different BIST PLA designs, are reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A design of programmable logic arrays with random pattern-testability

A testable design of programmable logic arrays (PLAs) with high fault coverage for random test patterns is introduced. Low area overhead is achieved by adding a mask array between the input-decoder and the AND array of the PLA. Several variations of the proposed approach are presented. The probability of fault detection and the test length are examined for both stuck-type and crosspoint-type faults to estimate the fault coverage achievable with the random patterns. >

Heuristic algorithm for the minimisation of generalised boolean functions

Generalised Boolean functions are useful in the design of programmable logic arrays. In this paper a heuristic algorithm suitable to minimise such functions is presented. The algorithm generates an irredundant cover by using a local approach to select generalised prime implicants. A benefit of such a method is that the preliminary generation of the set of all the generalised prime implicants is not required. Experimental results are presented, showing a favourable comparison with an already established minimisation algorithm as far as computing speed is concerned.