Design of new high-speed and low-energy dynamic PLA

Abstract

Programmable logic arrays (PLAs) are popular devices in the realisation of circuits as it can implement any Boolean function. This article proposes a dynamic complementary metal oxide semiconductor (CMOS) PLA based on NOR architecture that uses a secondary clock and feedback phenomena for low energy and high speed. Static power reduction is achieved by blocking the static current flow during evaluation period. The proposed design is simulated at 45 nm CMOS technology using CADENCE VLSI design tool. With respect to the latest low-energy and fastest PLA reported in the literature, the proposed design is 69% faster and consumes 73% less energy.