Power Circuit Design Research Articles

UIS Ruggedness of Parallel 4H-SiC MOSFETs

We have studied the UIS (Unclamped Inductive Switching) ruggedness of SiC MOSFETs in parallel. We show that UIS ruggedness of parallel MOSFETs is a function of the difference in their breakdown voltage (Δ-BVDSS). As expected, for large Δ-BVDSS UIS, ruggedness is dominated by the lower BVDSS transistor. Somewhat unexpectedly, for small enough Δ-BVDSS, UIS ruggedness is better than the sum of its two transistors. Specifically, the energy that parallel transistors of low Δ-BVDSS can sustain depends on the peak current and is 10%-20% higher than the sum of the energies of the individual transistors. We explain the physical mechanism of this effect and extend the concept to the case of more than 2 parallel transistors. These findings are important for the efficient design of power circuits with multiple die in parallel.

Harmonic compensation using a single phase active filter

This work presents the implementation of a single phase parallel active filter for harmonic compensation. The idea is to optimize the processed power by the active single-phase filter restricting the compensation only to harmonic currents without processing the linear reactive one. It is made a comparison study of processed power by a conventional active power filter compensating the entirely reactive power and another compensating only the harmonic contents. It is presented the control methodology employed, the power circuit design and the results obtained through a 500VA experimental prototype.

A low power circuit design of BLE baseband transmission data processing module

With the quickly development of the Internet of Things technology, Bluetooth (BLE) protocol has been increasingly adopted in consumer communication applications, industry communication utilization, and even positioning requirement, due to its advantages such as low power consumption, low cost, and low complexity. Especially the outstanding low power capability compared with other short-range communication protocol, many power limited AIoT (Artificial Intelligence IoT) devices select BLE as basic component. So, the low power, high performance, and small area BLE module become the key point of successful of whole AIoT system. In BLE system, the baseband data processing is the foundation. A good hardware circuit design of BLE baseband can improve BLE module performance and decrease power simultaneously. This paper analyzes the baseband data processing function of BLE in detail, and designs the baseband transmission data processing RTL circuit IP using Verilog HDL Hardware description language based on BLE protocol. The IP includes CRC verification module, whitening module and coding mapping function module. The RTL design is simulated and evaluated in workstation server with Synopsys VCS tool. The simulation results show that this design can achieve the Low-power BLE Bluetooth baseband function.

Power Circuit Design and Analysis of Controller For High-Power Axial Flux PMSM

Designing a high-power controller having high efficiency for permanent magnet motors is a challenge for developers in recent times and very few techniques are available. Design and analysis of power electronic drive for a high-power axial flux permanent magnet synchronous motor is presented in this paper. The motor under consideration here is having two outer stators and single permanent magnet rotor to drive the shaft. Control schemes and methodologies are the major concentration for research. Present paper explains a method to estimate the operational drive parameters and loss calculation according the selected power switches. In addition to this, thermal modelling is also important for designing a controller for high power machines. The hardware selection for high current switching operations is very critical for reliable and robust operation. Parts like IGBT module, gate driver, DC link capacitor, snubbers, current sensor sensitivities and estimation of losses are also critical along with control logic and processor. The importance of thermal analysis for high current switching drives is discussed and methodology for thermal analysis of power electronic devices is explained. The current work focuses on hardware level design of high-power drive for 150kW axial flux PMS motor.

A MOS-DTMOS Implementation of Floating Memristor Emulator for High-Frequency Applications

The work presented in this article focuses on designing a floating MOS-dynamic threshold voltage MOSFET (DTMOS)-based circuit to emulate a memristor. The proposed circuit consists of four transistors, including a DT-MOSFET and an external capacitor, which helps obtain high-frequency operations up to 3 MHz. This facilitates easier integration of the devices and monolithic IC fabrication. The correctness of the proposed emulator is validated by conducting various parametric analyses at different operating frequencies and process corners, and it generates acceptable pinched hysteresis loops (PHLs) at various frequencies. Furthermore, pre- and post-layout validation of the proposed emulator are also performed using Cadence Virtuoso with Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm process design kits (PDKs) to prove its effectiveness as a memristor. The area and power consumption of the proposed emulator are <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$157.48~\mu \text {m}^{2}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8.24~\mu \text {W}$ </tex-math></inline-formula> , respectively. The physical experiment of the proposed memristor emulator is performed using ALD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1106~n$ </tex-math></inline-formula> -channel MOSFETs to characterize its functionality as a real-life memristor. It is also used in designing a memristor-based application to showcase its applicability in power and area optimal circuit design.

Trends in volumetric-energy efficiency of implantable neurostimulators: a review from a circuits and systems perspective.

This paper presents a comprehensive review of state-of-the-art, commercially available neurostimulators. We analyse key design parameters and performance metrics of 45 implantable medical devices across six neural target categories: deep brain, vagus nerve, spinal cord, phrenic nerve, sacral nerve and hypoglossal nerve. We then benchmark these alongside modern cardiac pacemaker devices that represent a more established market. This work studies trends in device size, electrode number, battery technology (i.e., primary and secondary use and chemistry), power consumption and longevity. This information is analysed to show the course of design decisions adopted by industry and identifying opportunity for further innovation. We identify fundamental limits in power consumption, longevity and size as well as the interdependencies and trade-offs. We propose a figureof merit to quantify volumetric efficiency within specific therapeutic targets, battery technologies/capacities, charging capabilities and electrode count. Finally, we compare commercially available implantable medical devices with recently developed systems in the research community. We envisage this analysis to aid circuit and system designers in system optimisation and identifying innovation opportunities, particularly those related to low power circuit design techniques.

Novel Quantum-Dot Cellular Automata-Based Gate Designs for Efficient Reversible Computing

Reversible logic enables ultra-low power circuit design and quantum computation. Quantum-dot Cellular Automata (QCA) is the most promising technology considered to implement reversible circuits, mainly due to the correspondence between features of reversible and QCA circuits. This work aims to push forward the state-of-the-art of the QCA-based reversible circuits implementation by proposing a novel QCA design of a reversible full adder\full subtractor (FA\FS). At first, we consider an efficient XOR-gate, and based on this, new QCA circuit layouts of Feynman, Toffoli, Peres, PQR, TR, RUG, URG, RQCA, and RQG are proposed. The efficient XOR gate significantly reduces the required clock phases and circuit area. As a result, all the proposed reversible circuits are efficient regarding cell count, delay, and circuit area. Finally, based on the presented reversible gates, a novel QCA design of a reversible full adder\full subtractor (FA\FS) is proposed. Compared to the state-of-the-art circuits, the proposed QCA design of FA\FS reversible circuit achieved up to 57% area savings, with 46% and 29% reduction in cell number and delay, respectively.

The Matrix Model of Discrete Matching Elements for HF Computational Automatic Tuning Units

The article is devoted to a new and relevant direction in the HF communication technology - the construction of high-speed computational antenna tuning units (ATU). The implementation of automatic ATU requires the designing of power circuits models adequate, as practice shows, the construction of models to physical reality in order to ensure their controllability. Practically powerful device elements are not in fact concentrated, the distributed nature of their parameters is noticeably manifested in the HF range. Matching ATU on the base of antenna input impedance measuring involves forming of accurate control commands for the elements, especially in conditions where the settings are narrow-band. A new approach to the description of a power circuit discrete elements transforming properties using the theory of linear passive four-pole and matrices, which has the ultimate accuracy, is proposed. A method to form a matrix description of on-off discrete elements of a power circuit based on the results of characteristic field measurements of the mounted device is presented. This approach made it possible to significantly reduce the amount of tabulated data describing the functional dependences of the complex coefficients of wave transmission matrices and to “smooth out” the experimental error. Complex cases are considered, which are of the greatest interest for practice - options for a four-pole cascade and parallel connection of reactive elements in the branches of the power circuit. The current state of computer technology makes it possible to sharply increase the complexity of the mathematical models used. The matrix model takes into account a significant variety of operating factors and does not require them to be “customized” to existing analytical methods. The adequacy, in this simulation, is determined by practical needs that arise in the design of power circuits of matching antenna devices and their tuning algorithms. In fact, the model is considered adequate if the errors in the calculation of the response function according to the model do not exceed the errors in its experimental determination. The proposed matrix approach made it possible to significantly improve the accuracy of modeling, while the error does not exceed 1 %. Also, this approach allows to find several options for setting a given quality and choose the best one for any parameter, while reducing the duration of the process up to 25 times. At the additional metrological advantages appeared in such devices serial production.

Design of a bidirectional DC/DC converter for a hybrid electric drive system with dual-battery storing energy

Electric vehicles are projected to play an important role in the present and ensuing transportation as global environmental and energy issues become more serious. Looking into the growing popularity of electric vehicles, we need to pay even more attention to battery energy storage systems. Electric vehicles in the traditional sense rely on a battery to provide electricity. Influential requirements (acceleration and braking) will deteriorate the battery, or it may not be feasible to use it at all in some instances, due to the battery’s compactness. This paper proposes a Bidirectional DC/DC Converter topology and investigates its operation modes. The proposed converter can be used in hybrid electric vehicles. Hybrid electric vehicles use this converter type to connect a primary battery (ES1), an extra battery (ES2), and an adjustable voltage bus. Both step-up (i.e., Dual-source low-voltage powering mode) and step-down (i.e., energy-regenerating high-voltage dc-link mode) modes of operation are possible with the proposed converter, allowing bidirectional power flow. Furthermore, the model can handle the flow of electricity between any two low-voltage sources. For the proposed Bidirectional DC/DC Converter, two ways of power transmission, circuit design, and operation modes are analyzed. A MATLAB-Simulink model of the proposed, and the system is developed based on a Digital Signal Processor flow chart, and the results of the simulation as well as the performance of the system are discussed.

The Role of Frequency and Duty Cycle on the Gate Reliability of p-GaN HEMTs

In this letter, we present an extensive analysis on the role of both switching frequency (ranging from 100 kHz to 1 MHz) and duty cycle (from 10% to 90%) on the time-dependent gate breakdown of high electron mobility transistors (HEMTs) with Schottky metal to p-GaN gate. More specifically, results show how the gate lifetime of GaN HEMTs increases by reducing the frequency and the duty cycle of the stressing gate signal (VG). Such behavior is ascribed to the OFF-time, which is responsible to alter the electrostatic potential in the p-GaN layer during the rising phases of VG (from OFF- to ON-state). Findings of this analysis are useful both for further technology improvement and for GaN-based power circuit designers.

Low Power ALU using Wave Shaping Diode Adiabatic Logic

The evolution of portable electronic devices and their widespread application has led to an increased focus on power dissipation as one of the critical parameters. An increase in functionality requirement and design complexity on a single chip has resulted in increased power dissipation. High power dissipation has motivated study and innovation on low power circuit design techniques. Adiabatic logic has been studied as one of the design techniques to reduce power dissipation by reusing the power that was getting dissipated in conventional designs. This paper presents the application of Wave Shaping Diode Adiabatic Logic (WSDAL) to implement an ALU and analyse the improvement in power dissipation as compared to the conventional CMOS design. The WSDAL design uses a slow and time-fluctuating 2-phase sinusoidal Power Clock (PC), which supplies power as well as a clock to the designs. WSDAL uses an Ultra-Low Power Diode (ULPD) structure that operates as a wave shaping device and reduces glitches at the output. The design has been implemented in OrCAD Capture and simulated using Pspice in TSMC 180nm technology. The simulations were performed at 200MHz PC frequency and power dissipation was studied over a range of voltages from 1.4V to 2.2V. The simulations show that WSDAL ALU dissipates less power than the CMOS design. This study indicates that WSDAL-based designs have the potential to be deployed for power dissipation reduction in portable devices.

Low power architecture of logic gates using adiabatic techniques

The growing significance of portable systems to limit power consumption in ultra-large-scale-integration chips of very high density, has recently led to rapid and inventive progresses in low-power design. The most effective technique is adiabatic logic circuit design in energy-efficient hardware. This paper presents two adiabatic approaches for the design of low power circuits, modified positive feedback adiabatic logic (modified PFAL) and the other is direct current diode based positive feedback adiabatic logic (DC-DB PFAL). Logic gates are the preliminary components in any digital circuit design. By improving the performance of basic gates, one can improvise the whole system performance. In this paper proposed circuit design of the low power architecture of OR/NOR, AND/NAND, and XOR/XNOR gates are presented using the said approaches and their results are analyzed for powerdissipation, delay, power-delay-product and rise time and compared with the other adiabatic techniques along with the conventional complementary metal oxide semiconductor (CMOS) designs reported in the literature. It has been found that the designs with DC-DB PFAL technique outperform with the percentage improvement of 65% for NOR gate and 7% for NAND gate and 34% for XNOR gate over the modified PFAL techniques at 10 MHz respectively.

A new technique to check the correct mounting of the power module heatsinks

Temperature management is a non-secondary aspect in the design of power circuits and systems. As a matter of facts, changes in the junction temperature have significant effects on the semiconductor device behavior; furthermore, a high junction temperature accelerates the failure mechanisms of power devices used in the power module and reduces their lifetime. Therefore, it is often necessary to introduce a suitable heat dissipation system able to keep the junction temperature within the device operating limits. Passive heatsinks represent the most widely used strategy. However, an incorrect mounting of the heatsink may cause an unacceptable junction temperature increase in a power module. Even though the heatsink was initially properly assembled, it may be affected by defects during its working lifetime. Thus, it is necessary to devise effective strategies for testing the heatsink mounting at the end of the printed circuit board production and during the operational phase. In this paper, a method to test the heatsink mounting on power module is discussed. The proposed solution does not require thermal measurements, but only electrical ones and can be performed both at the end of the power module production, by means of an automatic test equipment, and in mission using a dedicated test circuit included in the system. The method was experimentally assessed on a DC-DC buck converter, validating the proposed solution.

A New Hybrid Pulsed Power Circuit Topology for Gas Laser Applications

A major decision surrounding the design of pulsed power circuits for gas lasers is the choice between a thyratron and solid-state switches. The thyratron is a mature device technology whose cost is increasing. The ratings of solid-state switches still do not match those of a thyratron. Pulse transformer and pulse compression circuits must be added to overcome the lower ratings of solid-state switches leading to a higher parts count and cost. This article proposes a new solid-state pulse power topology called the hybrid circuit topology to address the parts count and cost issue. The hybrid circuit makes use of a combination of capacitive and inductive energy storage to reduce the time required to transfer the energy from the transformer primary to the secondary side. This ultimately reduces the quantity of magnetic material used in the pulse compression circuit.

Trends in Design of Low Power Circuits Using Level Shifting Buffers for Multi Supply Systems

Power and performance efficiencies are the most important design parameters in system – on - chip design. Numbers of methods were developed for reducing the power and delay by reducing supply voltage and multi supply voltages. Multiple supply voltage designs need voltage level conversions between multiple voltage domains. This is achieved by the application of voltage level shifter (LS) circuits. LSs are an interfacing circuit which interconnects low core voltage to high core voltage and vice versa. LS ease communication among diverse modules. However literature reported that the conventional LSs suffer from delay variation due to dissimilar current driving transistors along with high power dissipation. This paper presents the identification of limitations and design aspects of existing LSs through an extensive literature survey and to project the current state of LSs. This study concentrates on multiple supply voltages, power consumption, and speed of processing in ICs. The detailed literature review is expected to pave way for addressing the issues and challenges related to LSs and helps in design and development of efficient low-power multivoltage LSs in the design aspects of VLSI circuits.

A Method for Selection of Power MOSFETs to Minimize Power Dissipation

A balance between static and dynamic losses of a power MOSFET is always desirable for accomplishing the maximum efficiency for a specific power converter. The standard semiconductor theory suggests that a minimum power dissipation in a MOSFET can be achieved by selecting a specific device active area. However, for power circuit designers, the active device area is unknown given that only datasheet parameters are available. Hence, in this paper, we propose a simple method, based on semiconductor theory, to select optimum power MOSFET from a family of MOSFETs using only datasheet parameters. By applying this optimization method to the specific power supply circuit under development, power engineers can select the best transistors to yield lowest power losses for the systems under development.

Guest Editorial Special Issue on Design and Testing Methods of Power Electronics Components and Circuits

Safe and reliable operation is always a crucial consideration in many important applications of power electronics. Nowadays, the working conditions or mission profiles of power electronics components/systems are becoming intensive and complicated. In order to ensure cost-effectiveness with more confidence in the safety and reliability performances, it is important to understand the loading and failure behaviors, as well as the limits of components/circuits in practical use. Under this scenario, the comprehensive verification and optimization from components up to systems are essential, especially when the power level is increasing and the competition in cost and performance is becoming severe in various applications.

Application of a resistive mutual-inductance fault current limiter in VSC-based HVDC system

The high DC fault current is a major challenge in voltage source converter (VSC)-based high voltage direct current (HVDC) systems. Direct-current circuit breakers (DCCBs) are used in these systems to protect the transmission lines against the DC fault current. However, they require large capacity and fast breaking speed to handle the DC fault current in VSC-based HVDC systems. Fault current limiters (FCLs) can be provide a reliable option to alleviate these issues. In this paper, a resistive mutual-inductance fault current limiter (RMFCL) is proposed to restrict the DC fault current in HVDC systems. It is based on the conventional mutual-inductance FCL that its power circuit is modified to reduce the DCCB requirements. The power circuit, principle operating and parameter design of the proposed RMFCL are presented. Then, the effectiveness of the proposed RMFCL is validated in a 3-terminal HVDC system in PSCAD/EMTDC system. Finally, its performance is compared with the parallel-resistor FCL (PRFCL), series-resistor FCL (SRFCL) and mutual-inductance FCL (MFCL). Comparative analysis demonstrates that the proposed RMFCL has superior performance in task of fault current amplitude, isolation time and energy absorption by the metal-oxide arrester (MOA) used in DCCB.

Low power circuit design using NCL based asynchronous method

The null convention logic (NCL) based circuit design methodology eliminates the problems related to noise, clock tree, electromagnetic interference and also reduces significant power consumption. In this paper, we would like to demonstrate the advantage of low power consumption of the NCL based asynchronous circuit design on a large design scale, thus we used the advanced encryption standard (AES) encryption design as an illustrative example. In addition, we also proposed two pipelined AES encryption models using the synchronous circuit design technique and the asynchronous circuit design technique based on NCL. Besides, these two models were realized by using version control system (VCS) tool to simulate and Design Compiler tool to synthesize parameters in power consumption, processing speed and area. The synthesis results of these two models indicated that power consumption of the NCL based asynchronous AES encryption model had a decrease of 71% compared with the synchronous AES encryption model. Moreover, we show the outstanding advantage of the power consumption of the NCL based asynchronous design model (a decrease of 91.12% and 93,23%) compared to the synchronous design model using clock gating technique and without using clock gating technique respectively.

A 0.25–0.4-V, Sub-0.11-mW/GHz, 0.15–1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps

This article presents an ultra-low-voltage phase-locked loop (ULVPLL) with the minimum supply voltage at 0.25 V. The offset dual-path loop architecture is proposed to relax the charge pump (CP) current matching requirement. Thus, no current mismatch suppression technique is required. This significantly mitigates the CP design challenges at such low supply voltage. In the two proposed dynamic CPs (DCPs), all the current sources, current mirrors, and op amps in the prior CPs are eliminated. Hence, the CP voltage headroom requirement is relaxed to make the DCP be suitable for sub-0.3-V operation; meanwhile, the CP power consumption and circuit design complexity are simultaneously reduced. Implemented in 40-nm CMOS with core area of 0.00873 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the 0.15-1.6-GHz ULVPLL is capable of operation under a 0.25-0.4-V supply voltage. The power efficiency is 0.106 mW/GHz from 1.6-GHz output (at 0.4-V supply) and 0.048 mW/GHz from 0.2 GHz (at 0.25-V supply). Measured spur level is -58.3 dBc at 100-MHz offset from 1.6-GHz output (at 0.4-V supply) and -48.5 dBc at 12.5-MHz offset from 200-MHz output (at 0.25-V supply).