Power Amplifier Design Research Articles

Design theory of broadband high‐efficiency continuous Class EF power amplifier based on new continuous factor

SummaryThis paper presents the design theory for continuous Class EF power amplifier (PA). This theory facilitates the implementation of broadband designs for high‐efficient Class EF PA. First, combining with the switching operating conditions and harmonic tuning technique, the drain waveform expressions of Class EF PA is derived. The corresponding third harmonic component can get its impedance in form of pure reactance, which simplifies the matching process while maintaining the efficiency. Second, a new continuous factor (CF) dedicated to the continuous Class EF PA can be obtained, with applying waveform mapping concept. The new CF expands the impedance point of Class EF PA into the impedance space. This greatly enhance the flexibility of broadband design. With this new theory, the design of broadband Class EF PA becomes very simple. As a verification, a Class EF PA operating at 2.4–3.8 GHz has been designed using CREE GaN HEMT CGH40010F. The PA can achieve the gain of 9.1–11.2 dB, the output power of 39.1–41.2 dBm, the PAE of 66.3%–74.1%, and the DE of 69.5%–76.2%. Both simulated and measured data show very good consistency and prove the rationality and validity of the proposed theory.

Design of broadband power amplifier based on loop-shaped filter matching structure

A method for designing a broadband high-efficiency power amplifier (PA) based on a novel loop-shaped filter matching structure is proposed in this paper. By combining a power amplifier matching circuit and a loop-shaped filter structure, a broadband high-efficiency PA based on a new harmonic matching structure is realized. The novel loop-shaped filter can control the second and third harmonics in a wide frequency range and has a specific control effect on higher-order harmonics, which can further expand the bandwidth of class-F PA and improve efficiency. To verify its feasibility, a power amplifier with a bandwidth of 1.6 GHz-3.4 GHz, a saturated output power greater than 41 dBm, a drain efficiency of 65% -72% with a gain greater than 10dB is designed and fabricated using GaN HEMT CGH40010F transistor.

A highly robust RF 65 nm CMOS power amplifier design using Quasi-Newton control algorithm for wireless system

This article reports a novel robust approach towards CMOS power amplifier (PA) using Quasi-newton (QN) control algorithm in 65 nm CMOS process which provides best performance parameters over redundant wide bandwidth ranging from 2.4 to 16.4 GHz frequency band. Each stage are designed and optimized using QN algorithm to get desired goals such as high linearity, small group delay variations and high PAE across the entire frequency band of interest. Moreover, pole-zeros compensation technique is adopted and derived to get better stability of the proposed PA. The simulation and measurement results of PA achieved a small signal power gain of 10.5–16.8 dB with input return loss of better than 10 dB over the frequency band of 2.4 GHz to 16.4 GHz. A small group delay variation of ±58 ps over full frequency band of operation is achieved by optimizing the design parametric analysis. It is also observed that within the frequency of 6.5 to 14.6 GHz, an excellent small group delay variation of only ±11 ps is achieved and this is due to stage-2 tuning compensation technique. It also demonstrates the achieved input power in 1 dB compression points are −3.1 to 4.3 dBm, leading to maximum power added efficiency of 36.3%, respectively. The proposed PA consumes a lower DC power of 20.5 mW under supply voltage of 1.5. In addition, Process, voltage and temperature (PVT) analysis is executed at different conditions in order to achieve a robustness of the proposed PA over the entire band of operation.

A novel design of graphene field-effect transistor-based out-phasing power amplifier

A novel design of graphene field-effect transistor-based out-phasing power amplifier

Nonlinear Capacitance Compensation Technique in a Linearity-Enhanced and Broadband GaN PA MMIC for Ku-/K-Band Applications

This article reports on exploiting a nonlinear capacitance compensation technique to achieve high linearity for power amplifier (PA) designs in III–V semiconductor technologies. High linearity is achieved by implementing multiple transistors with deliberate sizes and biasing to compensate for each nonlinear input capacitance behavior. Therefore, the composed PA core acts as one large device where each subdevice is biased individually. Moreover, this approach proves to be a reliable and easy way to improve PA linearity in III–V semiconductor technologies. The viability of this compensation is demonstrated by comparing it to other analog linearity improvement techniques such as derivative superposition. As a proof-of-concept prototype, a 17.2–20.2-GHz class-AB PA is designed in a space-evaluated 150-nm gallium nitride (GaN)-on-silicon carbide (SiC) process. Its capabilities are validated for various modulation bandwidths up to 500 MHz at several frequencies while delivering 32 dBm of output power. The measured third-order intermodulation distortion (IMD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_3$</tex-math> </inline-formula> ) and the fifth-order intermodulation distortion (IMD <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_5$</tex-math> </inline-formula> ) are improved by 18 and 25 dB, respectively, compared to a class-AB design. The measured amplitude-to-phase (AM–PM) distortion of less than 0.07 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\circ$</tex-math> </inline-formula> is obtained over the entire bandwidth. Finally, noise-to-power ratio (NPR) results prove the linearity enhancement concept with values better than 15 dB up to maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\rm out}$</tex-math> </inline-formula> . All the results were measured without any applied digital predistortion (DPD).

CMOS Power Amplifier With Novel Transformer Power Combiner

A novel transformer combiner structure for wattlevel CMOS power amplifier design is presented in this letter. The proposed active skewered transformer (AST) utilizes the slab inductor as the secondary winding and overcomes the quality factor degradation issue when input cells are increased. Slab inductor has been previously used in the distributed active transformer (DAT) as the primary winding and achieved superior passive efficiency for the transformer combined CMOS power amplifier. However, we find that the slab inductor could be more beneficial as the secondary winding when we are aiming for higher output power from the CMOS power amplifier. The full-wave EM simulation has been performed and shows the advantage of AST over the conventional series-combining transformers (SCTs). Finally, a 2.4GHz CMOS power amplifier is designed based on the AST structure and fabricated in 0.18um CMOS process. The measured output power and power-added efficiency of the proposed power amplifier satisfying LTE specification with 5/20MHz bandwidth are recorded as 26.0/25.0dBm and 24.0/20.9%, respectively.

Power Amplifier Design for Ultrasound Applications.

A design analysis of the power amplifiers developed for ultrasound applications was conducted because ultrasound applications require different types of power amplifiers, which are one of the most critical electronic components in ultrasound systems. To generate acoustic signals using transducers, which are among the most important mechanical devices in ultrasound systems, an appropriate output voltage, current, or power signal must be produced by a power amplifier. Therefore, an appropriate design analysis of the power amplifier must be conducted to obtain the optimal performance from a transducer. In addition, because of new ultrasound research trends, such as ultrasound systems with other imaging modalities and wireless ultrasound systems, the selection of an appropriate power amplifier could improve the performance of an ultrasound system with other imaging and therapy modalities. This paper describes the design parameters of a power amplifier, including the gain, bandwidth, harmonic distortion, and efficiency. Each power amplifier has specific applications and limitations. Therefore, this review will assist design engineers and ultrasound researchers who need to develop or use power amplifiers in ultrasound applications.

Analytical Approach to Improve the Performance of a Fully Integrated Class-F Power Amplifier with 0.13 µm BiCMOS Technology Using Drain–Bulk Capacitor Modulation

This article reports a novel technique based on drain–bulk capacitor modulation to improve the performance design of a class-F power amplifier (PA) used in low-power transceivers based on the I-Q amplitude modulation technique considering linearity–efficiency–miniaturization trade-offs. This idea is carried out by implementing a tuned capacitor in parallel with a cascode transistor on the output of the power stage to enhance the shape of the voltage–current amplitudes of the class-F PA by creating a new harmonic current component. Simulated results were obtained for the power back-off region of the proposed configuration, with an output power, power gain and power-added efficiency of 8 dBm (+ 5 dBm)B, 19 dB (+ 5 dB)B and 45% (+ 5% to 10%)B, respectively. In addition, post-layout simulations revealed a similar level of output power, a power gain of a 20 dB and a 28% power-added efficiency for an added capacitance equal to 1.3 pF. Class-F PA is implemented on a 732×605 μm2 chip’s surface. (B: indicates the improved values in the power back-off region).

A Ku-Band Broadband Stacked FET Power Amplifier Using 0.15 μm GaAs pHEMT.

To meet the application requirements of broadband radar systems for broadband power amplifiers, a Ku-band broadband power amplifier (PA) microwave monolithic integrated circuit (MMIC) based on a 0.15 µm gallium arsenide (GaAs) high-electron-mobility transistor (HEMT) technology is proposed in this paper. In this design, the advantages of the stacked FET structure in the broadband PA design are illustrated by theoretical derivation. The proposed PA uses a two-stage amplifier structure and a two-way power synthesis structure to achieve high-power gain and high-power design, respectively. The fabricated power amplifier was tested under continuous wave conditions, and the test results showed a peak power of 30.8 dBm at 16 GHz. At 15 to 17.5 GHz, the output power was above 30 dBm with a PAE of more than 32%. The fractional bandwidth of the 3 dB output power was 30%. The chip area was 3.3 × 1.2 mm2 and included input and output test pads.

Ultra-wideband CMOS power amplifier for wireless body area network applications: a review

&lt;span lang="EN-US"&gt;A survey on ultra-wideband complementary metal-oxide semiconductor (CMOS) power amplifiers for wireless body area network (WBAN) applications is presented in this paper. Formidable growth in the CMOS integrated circuits technology enhances the development in biomedical manufacture. WBAN is a promising mechanism that collects essential data from wearable sensors connected to the network and transmitted it wirelessly to a central patient monitoring station. The ultra-wideband (UWB) technology exploits the frequency band from 3.1 to 10.6 GHz and provides no interference to other communication systems, low power consumption, low-radiated power, and high data rate. These features permit it to be compatible with medical applications. The demand target is to have one transceiver integrated circuit (IC) for WBAN applications, consequently, UWB is utilized to decrease the hardware complexity. The power amplifier (PA) is the common electronic device that employing in the UWB transmitter to boost the input power to the desired output power and then feed it to the antenna of the transmitter. The advance in the design and implementation of ultra-wideband CMOS power amplifiers enhances the performance of the UWB-transceivers for WBAN applications. A review of recently published CMOS PA designs is reported in this paper with comparison tables listing wideband power amplifiers' performance.&lt;/span&gt;

Compact 40% Fractional Bandwidth Doherty PA With Input Group Delay Engineering

This letter presents a wideband Doherty power amplifier (DPA) design based on the control of the relative input group delay between the carrier and peaking amplifiers. By reaching an appropriate input phase variation over the target bandwidth, frequency dispersion of load modulation is minimized and a less dispersive DPA at peak power is achieved. To validate this approach, a compact DPA with 50-dBm peak power is developed and shows 51%–57% drain efficiency at 8-dB output power back-off (OBO) with a small-signal gain of 14.4–17 dB over 1.8–2.7 GHz which represents 40% fractional bandwidth (FBW). Linearization of the prototype is proven using DPD correction with ACPR below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 60 dBc measured in single-band scenarios. Moreover, under 400 MHz of instantaneous bandwidth, the proposed DPA achieves ACPR below <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 53 dBc with an average efficiency of 48%.

On the design considerations of solid‐state power amplifiers for satellite communications: A systems perspective

SummaryConventional solid‐state power amplifier (SSPA) design approach isolates radio frequency (RF) design from communication theory. In this paper, a unified SSPA design approach is proposed, which optimizes SSPA parameters (bias voltage and input RF signal power) to minimize total DC power consumption while satisfying received SNR constraint specified by the link budget. The effect of SSPA nonlinearity is quantified by the error vector magnitude measured at its output and the corresponding received SNR degradation is analyzed. Using the quantitative metrics for received SNR, it is possible to evaluate highly nonlinear SSPA classes such as Class‐B or deep‐Class AB, which are normally not considered in conventional SSPA design approach to be used in satellite communication applications.

Design and fabrication of a GaN HEMT power amplifier based on hidden Markov model for wireless applications.

Improvement of power amplifier's performance is the desired topic in communication systems. There are many efforts are made to provide good input and output matching, high efficiency, sufficient power gain and appropriate output power. This paper presents a power amplifier with optimized input and output matching networks. In the proposed approach, a new structure of the Hidden Markov Model with 20 hidden states is used for modeling the power amplifier. The widths and lengths of the microstrip lines in the input and output matching networks are defined as the parameters that the Hidden Markov Model should optimize. For validating our algorithm, a power amplifier has been realized based on a 10W GaN HEMT with part number CG2H40010F from the Cree corporation. Measurement results have shown a PAE higher than 50%, a Gain of about 14 dB, and input and output return losses lower than -10 dB over the frequency range of 1.8-2.5 GHz. The proposed PA can be used in wireless applications such as radar systems.

Over Octave Hybrid Continuous Modes Power Amplifier Design Based on Modified Real Frequency Technique

In this paper, a design method for an over octave hybrid continuous mode power amplifier (PA) based on modified real frequency technique (MRFT) is proposed. The extended continuous class-F/F-1 modes greatly expand the design space, which provides the possibility of over octave design, the optimal impedances at internal current-generator (I-Gen) plane and package plane are investigated. Then a novel broadband matching network based on MRFT is presented for impedance match. To verify the proposed methodology, an over octave PA with radial stub is fabricated and measured. The PA achieves a bandwidth of 133% from 0.8 GHz to 4 GHz, over this frequency range, the drain efficiency is 58.3-68.7% and largesignal gain is greater than 9.6 dB.

Design of Ultra-Wideband Doherty Power Amplifier Using a Modified Combiner Integrated with Complex Combining Impedance.

To be compatible with future wireless communication systems, it is very necessary to extend the bandwidth of the Doherty power amplifier (DPA). In this paper, a modified combiner integrated with a complex combining impedance is adopted to enable an ultra-wideband DPA. Meanwhile, a comprehensive analysis is performed on the proposed method. It is illustrated that the proposed design methodology can provide power amplifier (PA) designers with more freedom in implementing ultra-wideband DPAs. As a concept of proof, a DPA working over 1.2-2.8 GHz (a relative bandwidth of 80%) is designed, fabricated and measured in this work. Experimental results showed that the fabricated DPA delivers a saturation output power of 43.2-44.7 dBm with a gain of 5.2-8.6 dB. Meantime, the fabricated DPA achieves a saturation drain efficiency (DE) of 44.3-70.4% and a 6 dB back-off DE of 38.7-57.6%.

Efficient GaN-on-Si Power Amplifier Design Using Analytical and Numerical Optimization Methods for 24–30 GHz 5G Applications

This paper presents the design procedure of an efficient compact monolithic microwave integrated circuit power amplifier (MMIC PA) in a 0.1 μm GaN-on-Si process for 5G millimeter-wave communication. Load/source-pull simulations were conducted to correctly create equivalent large-signal matching models for stabilized power cells and to determine the optimal impedance domain. The shorted stub with bypass capacitors minimizes the transistor’s output reactance, simplifying the matching objective to an approximate real impedance transformation (IT). With miniaturization as the implementation guide, explicit formulas and tabulated methods based on mathematical analysis were applied to synthesize the filtering matching networks (MNs) for the input and output stages. In addition, a CAD-dependent numerical optimization approach was used for the interstage MN that needs to cope with high IT ratio and complex loads. The continuous-wave (CW) characterization for the proposed two-stage PA demonstrated 19.8 ± 0.7 dB of small-signal gain, very flat output power (Pout) and power-added efficiency (PAE) at 4 dB gain compression of 32–32.4 dBm and 34–34.6%, respectively, over 24–30 GHz, with 37.1% of peak PAE at mid-frequency.

Design of an Outphasing Power Amplifier Using Complex Combining Method for Broadband Application

This letter presents the design of a broadband outphasing power amplifier (OPA) based on complex combining impedance. The complex combining impedance is realized using a post-matching network (PMN) and is utilized to compensate for the frequency dispersion of the active load modulation in the OPA. It is illustrated for the first time that the bandwidth of an OPA can be extended by elaborately designing the complex combining impedance. To validate the proposed method, a broadband OPA operating over 1.7–2.2 GHz is designed and implemented. Measurement results show the fabricated OPA achieves a saturation power of 43.1–44.3 dBm, a saturation drain efficiency (DE) of 63.4%–78.4%, and a 6-dB back-off DE of 45.5%–70.4% in the interested frequency band.

High-Efficiency 200-GHz Neutralized Common-Base Power Amplifiers in 250-nm InP HBT

The analysis, design, and measurement of two Indium Phosphide (InP) heterojunction bipolar transistor (HBT) power amplifier (PA) designs are presented at G-band with record efficiency. A pseudo-differential common-base (CB) stage with neutralization capacitors and low-loss coupled-line balun (CLB) improve the gain and reduce matching loss. A single-stage design achieves 8.3 to 12.7-dBm output power and 7.7 to 17.3% power-added efficiency (PAE) over 180 to 220 GHz. The use of compact baluns allows the design to occupy only 0.011mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with power density of 1.69 W/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . A 3-stage, 4-way power-combined PA delivers 16.6 to 19.7-dBm output power and 6.5 to 13% PAE over 185 to 210 GHz.

Design of a broadband power amplifier based on high‐efficiency impedance space

SummaryWe propose a broadband high‐efficiency power amplifier (PA) with output power between 42.6 and 44.7 dBm, drain efficiency (DE) over 62%, and power additional efficiency (PAE) over 52% in the 2.3–3.5GHz frequency band. This PA effectively combines the high‐efficiency characteristics of class‐F PAs with the advantages of controlling the second harmonic for obtaining high efficiency at large bandwidth. The Dual Band Harmonic Control and Matching Network (DBHCN) realizes the conversion from 50 Ω to high‐efficiency impedance space (HEIS) while controlling the high‐order harmonics in different frequency bands. The proposed PA can be used for the fifth‐generation mobile communication technology (5G) base stations and broadband radars.

Design of Class F Power Amplifier for Sub 6 GHz

Class F power amplifiers increasingly have widespread use cases in the modern portable mobile communications and higher efficiency operation due to base station. This paper focuses on the design of sub 6 GHz class-F Power Amplifiers (PA) to ensure maximum output power and gain using Gallium nitride– High Electron Mobility Transistor (GaN HEMT). The work also aims to analyze stability and Power Added Efficiency (PAE) using Advanced Design System (ADS) software. Simulations for DC characteristics of the GaN HEMT transistor are performed, stability circles are simulated, and stability factor values have been noted, using ADS software. Stability analysis involves measurements to examine the conditions that may lead to unstable behavior of the PA. The load pull analysis followed by impedance matching is done to transfer maximum power from amplifier stage to load. The input and output network has been designed using transmission lines and incorporated in the final circuit of the PA design. Using the LineCalc tool, the values of electrical parameters are used in the respective MLIN and TLIN circuits, and the respective matching networks are designed at the input side and output side. The amplifier stability factor is 2.276 and the maximum PAE is 65.75%. The maximum output is 39.83 dBm. The layout for the PA network using ADS software has been obtained.