Operating System Design Research Articles

SpaceJMP

Memory-centric computing demands careful organization of the virtual address space, but traditional methods for doing so are inflexible and inefficient. If an application wishes to address larger physical memory than virtual address bits allow, if it wishes to maintain pointer-based data structures beyond process lifetimes, or if it wishes to share large amounts of memory across simultaneously executing processes, legacy interfaces for managing the address space are cumbersome and often incur excessive overheads. We propose a new operating system design that promotes virtual address spaces to first-class citizens, enabling process threads to attach to, detach from, and switch between multiple virtual address spaces. Our work enables data-centric applications to utilize vast physical memory beyond the virtual range, represent persistent pointer-rich data structures without special pointer representations, and share large amounts of memory between processes efficiently. We describe our prototype implementations in the DragonFly BSD and Barrelfish operating systems. We also present programming semantics and a compiler transformation to detect unsafe pointer usage. We demonstrate the benefits of our work on data-intensive applications such as the GUPS benchmark, the SAMTools genomics workflow, and the Redis key-value store.

SpaceJMP

Memory-centric computing demands careful organization of the virtual address space, but traditional methods for doing so are inflexible and inefficient. If an application wishes to address larger physical memory than virtual address bits allow, if it wishes to maintain pointer-based data structures beyond process lifetimes, or if it wishes to share large amounts of memory across simultaneously executing processes, legacy interfaces for managing the address space are cumbersome and often incur excessive overheads. We propose a new operating system design that promotes virtual address spaces to first-class citizens, enabling process threads to attach to, detach from, and switch between multiple virtual address spaces. Our work enables data-centric applications to utilize vast physical memory beyond the virtual range, represent persistent pointer-rich data structures without special pointer representations, and share large amounts of memory between processes efficiently.

SpaceJMP

Memory-centric computing demands careful organization of the virtual address space, but traditional methods for doing so are inflexible and inefficient. If an application wishes to address larger physical memory than virtual address bits allow, if it wishes to maintain pointer-based data structures beyond process lifetimes, or if it wishes to share large amounts of memory across simultaneously executing processes, legacy interfaces for managing the address space are cumbersome and often incur excessive overheads. We propose a new operating system design that promotes virtual address spaces to first-class citizens, enabling process threads to attach to, detach from, and switch between multiple virtual address spaces. Our work enables data-centric applications to utilize vast physical memory beyond the virtual range, represent persistent pointer-rich data structures without special pointer representations, and share large amounts of memory between processes efficiently. We describe our prototype implementations in the DragonFly BSD and Barrelfish operating systems. We also present programming semantics and a compiler transformation to detect unsafe pointer usage. We demonstrate the benefits of our work on data-intensive applications such as the GUPS benchmark, the SAMTools genomics workflow, and the Redis key-value store.

M3

In the last decade, the number of available cores increased and heterogeneity grew. In this work, we ask the question whether the design of the current operating systems (OSes) is still appropriate if these trends continue and lead to abundantly available but heterogeneous cores, or whether it forces a fundamental rethinking of how systems are designed. We argue that: 1. hiding heterogeneity behind a common hardware interface unifies, to a large extent, the control and coordination of cores and accelerators in the OS, 2. isolating at the network-on-chip rather than with processor features (like privileged mode, memory management unit, ...), allows running untrusted code on arbitrary cores, and 3. providing OS services via protocols over the network-on-chip, instead of via system calls, makes them accessible to arbitrary types of cores as well. In summary, this turns accelerators into first-class citizens and enables a single and convenient programming environment for all cores without the need to trust any application. In this paper, we introduce network-on-chip-level isolation, present the design of our microkernel-based OS, M3, and the common hardware interface, and evaluate the performance of our prototype in comparison to Linux. A bit surprising, without using accelerators, M3 outperforms Linux in some application-level benchmarks by more than a factor of five.

M3

In the last decade, the number of available cores increased and heterogeneity grew. In this work, we ask the question whether the design of the current operating systems (OSes) is still appropriate if these trends continue and lead to abundantly available but heterogeneous cores, or whether it forces a fundamental rethinking of how systems are designed. We argue that: 1. hiding heterogeneity behind a common hardware interface unifies, to a large extent, the control and coordination of cores and accelerators in the OS, 2. isolating at the network-on-chip rather than with processor features (like privileged mode, memory management unit, ...), allows running untrusted code on arbitrary cores, and 3. providing OS services via protocols over the network-on-chip, instead of via system calls, makes them accessible to arbitrary types of cores as well. In summary, this turns accelerators into first-class citizens and enables a single and convenient programming environment for all cores without the need to trust any application. In this paper, we introduce network-on-chip-level isolation, present the design of our microkernel-based OS, M3, and the common hardware interface, and evaluate the performance of our prototype in comparison to Linux. A bit surprising, without using accelerators, M3 outperforms Linux in some application-level benchmarks by more than a factor of five.

An energy-efficient design of microkernel-based on-chip OS for NOC-based manycore system

The chip multiprocessor is the most prolific processor design because its many cores enhance system performance. Network on chip (NOC) has been proposed as a promising model to solve the connection problem of the cores. However, a new challenge consists of fully benefiting from the on-chip network and the cores. In this paper, we propose a novel energy-efficient design of a microkernel-based on-chip operating system for an NOC-based manycore system. The operating system (OS) is partitioned into the microkernel and the other OS modules. They are distributed on the network to provide services to the user programs. Our experimental results show that our design can improve system performance with reduced power consumption.

Analysis of the robustness of terminal turnaround arrangements for railways

The application of Lean principles to terminus operations of high-speed railways has the potential of enhancing the efficiency of resource usage during both the construction and operation periods, through faster turnarounds and, hence, a reduced space requirement thanks to fewer platform tracks being needed. However, this greater efficiency must not be allowed to result in less robust services. The robust design of products and processes has been studied extensively in the manufacturing industry. By contrast, the robustness of high level railway operational concepts and system design has been investigated rarely. In this study, Taguchi methods that originated in the manufacturing industry are applied to a robustness assessment of system designs in the context of railway operations. The approach is used to assess terminus designs with different numbers of platform tracks, layouts with particular conflict patterns, minimum required turnaround times and signaling facility capability. The authors use a Monte Carlo simulation with statistical delay distributions. The simulation results show that the signaling system's capability is the most important factor in achieving high capacity and that the robustness of railway terminus operations is not affected by adopting faster turnaround and having fewer platform tracks at termini. Finally, some suggestions for future planning are presented.

CONTROL INTELLECTUALIZATION DESIGN FOR PRODUCTION PROCESS PREPARATION OF SECTION MILL

An increase of production activity effi ciency of an enterprise can be reached by effi ciency increase of the management decisions making process. Modern highly intellectual management systems are based on the principles of fuzzy logic and allow not only to process the large volumes of versatile and unstructured information, but also to make decisions quickly in conditions of invariance and insuffi ciency of data. Such systems usage and adaptation to real working conditions are main ways to increase the production effi ciency. The article describes the possibility of operational management system design. Such system is based on symbiosis between multi-level multi-agent systems and dynamic expert systems and is expected to be used for processes of section mill stand preparation and transfer, making and adjustment of the rolling plan under the conditions of interaction of all agents of a technological circuits.

On the Design and Evaluation of a Real-Time Operating System for Cache-Coherent Multicore Architectures

The uncontrolled use of the cache hierarchy in a multicore processor by real-time tasks may impact their worst-case execution times. Several operating system techniques have been recently proposed to deal with caches in a multiprocessor in order to improve predictability, such as cache partitioning, cache locking, and real-time scheduling. However, the contention caused by the cache coherence protocol and its implication for real-time tasks is still an open problem. In this paper, we present the design and evaluation of a real-time operating system for cache-coherent multicore architectures. The real-time operating system infrastructure includes real-time schedulers, cache partitioning, and cache coherence contention detection through hardware performance counters. We evaluate the real-time operating system in terms of run-time overhead, schedulability of realtime tasks, cache partitioning performance, and hardware performance counters usability. Our results indicate that: (i) a real-time operating system designed from scratch reduces the run-time overhead, and thus improves the realtime schedulability, when compared to a patched operating system; (ii) cache partitioning reduces the contention in the shared cache and provides safe real-time bounds; and (iii) hardware performance counters can detect when real-time tasks interfere with each other at the shared cache level. Scheduling, cache partitioning, and hardware performance counters together are a step-forward to provide real-time bounds in cache-coherent architectures.

Petri-net based modelling approach for ALFRED reactor operation and control system design

In this work, the Petri-net modelling approach applied to the control system design of the Advanced Lead Fast Reactor European Demonstrator (ALFRED) is presented, paying particular attention to the startup procedure. The reactor startup is the operational transient in which all the systems of the plant are brought from the cold shutdown condition to the full power mode, close to load-frequency control. In this phase, the several control actions to be taken need to be properly coordinated. To this end, the operational sequence which constitutes the reactor startup procedure has been described by adopting the Petri-nets approach, i.e., a useful formalism for the modelling and the analysis of Discrete Event Systems. Thanks to this quantitative representation, it is possible to easily derive the corresponding control scheme. In addition, the Petri-nets approach has been also exploited for the two-level control system architecture, namely a master system coordinates the operation of the plant by sending suitable signals to the slave system, in which feedback controllers are implemented. As a major outcome of this work, the procedure for the reactor startup and the transition to the full power mode has been simulated in order to assess the control system performance.

Aspects of designing and evaluating seasonal‐to‐interannual Arctic sea‐ice prediction systems

Using lessons from idealised predictability experiments, we discuss some issues and perspectives on the design of operational seasonal to inter‐annual Arctic sea‐ice prediction systems. We first review the opportunities to use a hierarchy of different types of experiment to learn about the predictability of Arctic climate. We also examine key issues for ensemble system design, such as measuring skill, the role of ensemble size and generation of ensemble members. When assessing the potential skill of a set of prediction experiments, using more than one metric is essential as different choices can significantly alter conclusions about the presence or lack of skill. We find that increasing both the number of hindcasts and ensemble size is important for reliably assessing the correlation and expected error in forecasts. For other metrics, such as dispersion, increasing ensemble size is most important. Probabilistic measures of skill can also provide useful information about the reliability of forecasts. In addition, various methods for generating the different ensemble members are tested. The range of techniques can produce surprisingly different ensemble spread characteristics. The lessons learnt should help inform the design of future operational prediction systems.

An analysis of trusted service manager development modes by mobile operating system designers in Taiwan

A trusted service manager (TSM) mediates between service providers, mobile network operators (MNOs), and the secure element (SE) issuer. As a facilitator to accelerate the development of the Near Field Communication (NFC) application ecosystem, such as mobile payments, e-tickets, etc., the TSM and its issues have received increased attention in recent years. In this study, the TSM development modes are analyzed under the challenges of mobile operating system designers (OSD) by an analytical network process. The research framework for developing a TSM is constructed by four main criteria and twelve sub-criteria through a literature review. Based on the authors’ previous work, five possible developing modes of TSMs are set as alternatives. An analytic network process (ANP) framework is proposed, and expert questionnaires are designed. Eighteen experts in NFC-related domains, including MNO, bank, smart card, and TSM stakeholders, were interviewed, and a proper developing mode for TSM in Taiwan was obtained. All these experts are in businesses related with TSM or are familiar with the TSM ecosystem.The analytical results not only include the ranks of four main criteria and twelve sub-criteria but also reveal that experts expect “Cooperation mode” to be the best alternative for developing a TSM in Taiwan. The explanations for the ranks are discussed with the current NFC ecosystem in Taiwan. The research framework for developing a TSM in this study is also expected to be applied to different countries, as developing modes of a TSM are generally multiple-criteria decision-making issues. Developing modes of a TSM for other countries could be implemented by changing the criteria, sub-criteria and alternatives of this research structure according to a country’s own political, NFC-related business environment or development stage of the NFC industry. In conclusion, this study provides academic and managerial implications of the results showing why “Cooperation mode” could be the best alternative to develop a TSM in Taiwan. This study’s contributions are as follows. First, an ANP network of TSM development is constructed, and it can be applied to other countries with similar developing mode analysis processes. Second, a proper developing mode of a TSM in Taiwan based on the views of different experts is uncovered.

Adaptive Instructor Operating Systems

Scenario-based training (SBT) environments are effective, carefully planned learning events that give trainees an opportunity to practice targeted skills in a variety of situations, while performance is monitored and assessed for feedback (Cannon-Bowers & Salas, 1998). However, SBT for teams can require a large number of instructors to man events, and can lead to high instructor workload. This paper describes a 5 year Science and Technology (S&T) effort that addressed challenges that instructors face in conducting SBT exercises in a team environment. We discuss the design of instructor operating systems (IOSs) that provides instructors with the ability to monitor scenarios, assess key performance indicators, and to remediate breakdowns in performance during team training. Further, we describe an effectiveness evaluation of the impact of an adaptive IOS on instructor performance and workload.

Self-adaptive corner detection on MPSoC through resource-aware programming

Multiprocessor system-on-chip (MPSoC) designs offer a lot of computational power assembled in a compact design. In mobile robotic applications, they offer the chance to replace several dedicated computing boards by a single processor, which typically leads to a significant acceleration of the computer-vision algorithms employed. This enables robots to perform more complex tasks at lower power budgets, less cooling overhead and, ultimately, smaller physical dimensions.However, the presence of shared resources and dynamically varying load situations leads to low throughput and quality for corner detection; an algorithm very widely used in computer-vision. The contemporary operating systems from the domain have not been designed for the management of highly parallel but shared computing resources.In this paper, we evaluate resource-aware programming as a means to overcome these issues. Our work is based on Invasive Computing, a MPSoC hardware and operating-system design for resource-aware programming. We evaluate this system with real-world algorithms, like Harris and Shi-Tomasi corner detectors. Our results indicate that resource-aware programming can lead to significant improvements in the behavior of these detectors, with up to 22 percent improvement in throughput and up to 20 percent improvement in accuracy.

A preliminary dynamic behaviors analysis of a hybrid energy storage system based on adiabatic compressed air energy storage and flywheel energy storage system for wind power application

Integrating energy storage system into wind system can mitigate the negative effects caused by the intermittent wind. In addition, the spectrum analysis of wind power implies that the hybrid energy storage system may have better performance on smoothing out the wind power fluctuations than the independent energy storage system. The main advantage of the hybrid energy storage system is the multi-response speeds. Also, the hybrid energy storage system often operates in the modes switch, partial load and frequent start/stop conditions. Thus, the dynamic behaviors of each devices and the assembly of hybrid energy storage system are important for the system operation and control system design. The design, off-design analysis and parametric analysis of a wind-hybrid energy storage system consisting an A-CAES (adiabatic compressed air energy storage) system and a FESS (flywheel energy storage system) based on spectrum analysis method are carried out in the previous paper (P Zhao et al., 2014). This paper will conduct a preliminary dynamic behaviors analysis of the proposed wind-hybrid energy storage system based on the dynamic models. The simulation results indicate that the total power of wind-hybrid energy storage system can fit the load requirement well, providing an efficient power management for wind power penetration.

Nested Kernel

Monolithic operating system designs undermine the security of computing systems by allowing single exploits anywhere in the kernel to enjoy full supervisor privilege. The nested kernel operating system architecture addresses this problem by "nesting" a small isolated kernel within a traditional monolithic kernel. The "nested kernel" interposes on all updates to virtual memory translations to assert protections on physical memory, thus significantly reducing the trusted computing base for memory access control enforcement. We incorporated the nested kernel architecture into FreeBSD on x86-64 hardware while allowing the entire operating system, including untrusted components, to operate at the highest hardware privilege level by write-protecting MMU translations and de-privileging the untrusted part of the kernel. Our implementation inherently enforces kernel code integrity while still allowing dynamically loaded kernel modules, thus defending against code injection attacks. We also demonstrate that the nested kernel architecture allows kernel developers to isolate memory in ways not possible in monolithic kernels by introducing write-mediation and write-logging services to protect critical system data structures. Performance of the nested kernel prototype shows modest overheads: <1% average for Apache and 2.7% for kernel compile. Overall, our results and experience show that the nested kernel design can be retrofitted to existing monolithic kernels, providing important security benefits.

Nested Kernel

Monolithic operating system designs undermine the security of computing systems by allowing single exploits anywhere in the kernel to enjoy full supervisor privilege. The nested kernel operating system architecture addresses this problem by "nesting" a small isolated kernel within a traditional monolithic kernel. The "nested kernel" interposes on all updates to virtual memory translations to assert protections on physical memory, thus significantly reducing the trusted computing base for memory access control enforcement. We incorporated the nested kernel architecture into FreeBSD on x86-64 hardware while allowing the entire operating system, including untrusted components, to operate at the highest hardware privilege level by write-protecting MMU translations and de-privileging the untrusted part of the kernel. Our implementation inherently enforces kernel code integrity while still allowing dynamically loaded kernel modules, thus defending against code injection attacks. We also demonstrate that the nested kernel architecture allows kernel developers to isolate memory in ways not possible in monolithic kernels by introducing write-mediation and write-logging services to protect critical system data structures. Performance of the nested kernel prototype shows modest overheads: <1% average for Apache and 2.7% for kernel compile. Overall, our results and experience show that the nested kernel design can be retrofitted to existing monolithic kernels, providing important security benefits.

THE POSSIBILITY OF USING ARTIFICIAL NEURAL NETWORKS WHEN PREDICTING TRAIN WORK TRAIN DIRECTIONS

Effective operational planning of the transportation process should be based on accurate forecasts of revenue trains, wagons, locomotives, freight, etc. This prediction can be realized with the help of modern mathematical method – apparatus of artificial neural networks. Neural networks have such properties as adaptive learning, self-organizing, summarizing, calculating in real time and resistance to disruption. The main applications of neural networks are functions approximation, associative memory, data compression, pattern recognition and classification, optimization problems, the management of complex processes and forecasting. The constituent elements of a formal neuron are х1, х2, …, хn – the network inputs, each of which is characterized by its weight w1, w2, …, wn, respectively. The adder Σ summarizes the input signals, the activation function f describes the neuron transition rule when new signals are received. According to connections architecture the neural networks can be grouped into two classes: feedforward networks, which graphs have no loops, and recurrent networks or networks with feedback. By the neural network training is understood a setting of the network architecture and weights for the effective implementation of the task. The learning methods can be divided into two groups: with the teacher and without a teacher. Neural networks can be used for real-time forecasting of the train arrival at the technical stations on the basis of known departure parameters of the trains: information about the time of departure from the neighboring technical station, the train weight, the data on seasonal and weekly uneven. While designing the neural network to solve a particular problem should be considered several variants differing in, for example, the number of neurons in the layers, the number of hidden layers, etc. The main indicators, by which can be made a comparison of the selected architectures of neural networks can be such parameters as the minimum error, as well as a high correlation coefficient between actual and calculated data. Thus, the artificial neural networks can be widely used in the design of operational traffic control systems since allows to receive an accurate prediction based on many factors and is relatively simple to design

Análisis y Diseño de Sistemas Multiagente Normativos Abiertos

This article summarizes the main contributions of the thesis titled "Engineering Regulated Open Multiagent Systems". This thesis is focused on the analysis and design of normative open systems using multiagent technology. Specifically this thesis offers: (1) a metamodel that allows especifying all the features of systems of this kind; (2) a methodology that covers the analysis through a detailed development process and specific guidelines that include the identification and formalization of the normative context of the system; (3) a CASE tool that integrates the design of the system with the formal verification of its normative context.

Time of Arrival range Based Wireless Sensor Localization in Precision Agriculture

Precision agriculture relies on information technology, whose precondition is providing real-time and accurate information. It depends on various kinds of advanced sensors, such as environmental temperature and humidity, wind speed, light intensity, and other types of sensors. Currently, it is a hot topic how to collect accurate information, the main raw data for agricultural experts, monitored by these sensors timely. Most existing work in WSNs addresses their fundamental challenges, including power supply, limited memory, processing power and communication bandwidth and focuses entirely on their operating system and networking protocol design and implementation. However, it is not easy to find the self-localization capability of wireless sensor networks. Because of constraints on the cost and size of sensors, energy consumption, implementation environment and the deployment of sensors, most sensors do not know their locations. This paper provides maximum likelihood estimators for sensor location estimation when observations are time-of arrival (TOA) range measurement.