MOSFET Design Research Articles

Optimal design of kelvin source SiC MOSFET based PFC considering inductor parasitic capacitance and source mutual inductance

SiC MOSFET with Kelvin source has the advantage of high switching speed due to the lack of common source parasitic inductance. However, the high switching speed will make the parasitic parameters affect the performance of PFC converter obviously. Thus, it is necessary to analyze the influence of parasitic parameters on PFC circuits. The input PF model and switching energy loss model are established considering the inductor parasitic capacitance, and the influence of inductor parasitic capacitance on input PF and switching energy loss is analyzed. The switching energy loss model was established considering source mutual inductance, and the influence of source mutual inductance on switching energy loss was analyzed. Then we obtained the optimum value range of inductor parasitic capacitance and Kelvin source mutual inductance. The simulation and experimental results are given to verify the correctness of the mathematical model and analysis.

(Invited) Vertical Gallium Nitride Mosfets for Electric Drivetrains

Wide-bandgap semiconductors have a significant advantage over conventional Si-based electronics by leveraging materials properties to achieve higher breakdown voltage, lower on-resistance, and high-frequency operation. For electric vehicle drivetrains, this translates to higher efficiency and power density, resulting in more miles driven per charge. This move towards wide-bandgap power electronics is necessary to achieve the U.S. Department of Energy (DOE) power electronics density target of 100 kW/L.Vertical gallium nitride-based power devices are expected to exceed Si and even SiC-based systems with the promise of increased performance and power density. Compared to lateral GaN devices, a vertical topology promotes more efficient scaling towards high-power applications, where both high voltage and high current are necessary. This talk describes our team’s effort towards developing vertical GaN MOSFETs. The results of Sandia’s first-generation device demonstrator serve as a milestone in the path of producing devices rated for 1200-V and 100-A operation.The vertical GaN trench MOSFET is unique compared to Si- or SiC-alternatives in that the doped layers comprising the source and body regions are grown by epitaxy rather than formed by ion implantation. Challenges with selective-area doping in GaN add additional complexity to the design of a trench MOSFET. In addition, the lack of a high-quality native oxide in GaN means that the gate dielectric must be deposited rather than thermally grown. The devices produced at Sandia rely on atomic-layer-deposited thin films for the gate dielectric (primarily Al2O3 or SiO2). First-generation results demonstrate devices capable of 400 mA/mm drain current, 108 on/off ratio, and a positive threshold voltage near 8 V. More recently, devices capable of blocking 500 V in the off-state have been demonstrated. Device failure in the off-state results from high fields in the gate dielectric, which can be minimized by reducing the trench etch depth or by increasing the voltage rating of the drift region. However, further shielding of the gate dielectric to achieve substantially higher off-state voltages requires significant changes to the device architecture which are reliant on selective-area doping. In addition, device-killing defects either from the starting substrate, the epitaxy, or defects introduced during processing limit yield for large-area devices and present a substantial obstacle to scale devices for high-current operation. Hence, methods for reducing cell pitch and increasing packing density are highly valued. In this talk, we will discuss the path forward for achieving higher breakdown voltages and high-current operation using GaN-specific strategies to achieve better performing devices, as well as some of the challenges for vertical GaN development. This work provides a foundational platform for developing next-generation power electronics that employ wide bandgap, gallium nitride semiconductors. This work was supported by the Electric Drivetrain Consortium managed by Susan Rogers of DOE’s Vehicle Technologies Office. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. Figure 1

A Novel Design of Heterojunction Double Ferroelectric MOSFET (HDF-MOSFET) with Steep Subthreshold Slope and High Ion/Ioff Current Ratio

In this work, three novel structures using ferroelectric material are designed and simulated. The proposed structures are Improved Priority, Single Ferro (SF-MOSFET), Double Ferro (DF-MOSFET), and Heterojunction Double Ferro (HDF-MOSFET), respectively. Unlike other structures, these structures have a contact gate and two ferroelectric layers, and an insulation layer between these layers. HfO2 is used instead of the common perovskite ferroelectric layers such as zirconium lead titanate (PbZrTiO3 ) and strontium bismuth tantalum (SrBi2 Ta2 O9 ), which makes it compatible with the CMOS process as well as the scalability of the device. Ferroelectric layers, Insulation and Ferroelectric layers are stacked (F-I-F). Placing double ferro layers in the form of a stack increases the polarization effects and improves the application of the structure in memory. The memory performance can be saved even after the power is turned off and the readout properties are not destructive for double ferroelectric stack. perovskite Lead Zirconium Titan ate (PZT) is chosen as the ferroelectric materials. The DF-MOSFET structure, value of on-state current Ion=10-2, off-state current Ioff=10-15, and memory Windows MW=0.9V for memory applications. In the barrier layer of HDF-MOSFET structure, from composite materials that have used TiO2 =60% and HfO2 =40%, the amount of Ion=10-4.8, Ioff=10-35.2 and Ion/Ioff = 2.51×1035 is obtained, which is a suitable application for high frequency.

Design of Hafnium Oxide (HfO<sub>2</sub>) Sidewall in InGaAs/InP for High-Speed Electronic Devices

The Indium Gallium Arsenide (InGaAs) based MOSFETs have been widely used in the research of high-speed devices with higher frequency. It has some application in the designing areas of power amplifiers. The InGaAs mainly have greater electron mobility and the lesser band gap in their compound makes them more suitable for developing high-speed devices. The Indium Gallium Arsenide compound-based MOSFETs are designed using the source/drain grown on a passive layer of Indium Phosphide substrate. This helps in reducing the power budget of the MOSFET and thereby reduces source and drain resistance. The re-grown layers over the bulk have serious issues such as parasitic capacitance and greater electrical field at the terminals of the gate along with the drain terminal. This results in a larger leakage current along with the terminals and thereby induces the degradation of the frequency of the application amplifiers. The high-ƙ dielectric along the gate terminal makes the device immune to leakage current for lesser frequency applications. The optimum material for the dielectric may be Hafnium (IV) Oxide – HfO2 which has been used as a sidewall in the proposed InGaAs MOSFET design. The device simulation was carried out in a way to evaluate the characteristics of the proposed designs. The results were submissive to the conventional MOSFETs in terms of output capacitance over the source and drain terminals, leakage current in the drain terminal, and improved frequency parameters. The results also suggested that the sidewall design over the gate terminal constitutes the frequency improvement without losing the power and current characteristics.

Zoomed Response Surface Method for Automatic Design in Parameters Optimization of Low-Voltage Power MOSFET

A new parameter optimization method using zoomed response surface (RS) is proposed for automatic design of low-voltage power MOSFET. Low-voltage MOSFET characteristics have been improved continuously considering with not only low power loss but also low cost to answer request to high-performance system. Complicated requirements lead long development schedule and low yield. Model-based design and machine learning are prospective method to answer the problem. However, reported methods require many simulation numbers (>1000) for training to obtain high accuracy, and it is difficult to optimize parameters considering the process margin at the same time. This article shows a simple design method using zoomed RS. Five parameters were automatically designed, taking account to process margin with simulation number of 130 only.

Design of Cylindrical Surrounding Double-Gate MOSFET With Fabrication Steps Using a Layer-by-Layer Approach

The semiconductors with nanometer-scale are subjected to various patterns and scaling using the latest technology. The most widely used methods are top-down approaches in the design of complex heterostructures. The top-down approach involves the photolithography to ion sequentially beaming of the materials. In this context, the alternative layer-by-layer approach with cylindrical structures has been discussed and supported by the subsequent results to make Cylindrical Surrounding Double-Gate (CSDG) MOSFETs in this research work. This method involves the making of cylindrical structures with high-resolution morphological structures of CSDG MOSFETs. The process has been described in detail to design the CSDG MOSFETs with high-ƙ dielectric materials to make them suitable for low-frequency RF applications. The fast modulation of the Single Nano Wire (SNW) has been adopted for complex heterostructure modeling. The high-ƙ dielectric materials are placed in between the spacer and the gate material to overcome the Short Channel Effects (SCEs). This method produces symmetrical and concentric cylindrical structures of the CSDG MOSFETs with suitable layers. The minimum layer thickness achieved is about 10 nm axial length along with the core of the SNW. This gives enough insight for the proposed cylindrical structure to fabricate over the core of 2DEG. In this type of structure development, many cylindrical structures with various properties can be designed. The parameters focused on the cylindrical structure will be periodic, non-periodic, symmetric, asymmetric structures, and gaps/dots of nanometer scale. This innovative method introduces the method of designing the symmetric CSDG MOSFET concerning the center core. In this work, the authors focus on the suitable novel technique of designing cylindrical structures with unique dimensions and physical properties using various semiconductor materials.

Design and Implementation of Efficient MOSFET’s Utilization Based Proposed Voltage Controlled Oscillator

Ring oscillator is a device which consists of NOT gates connected in the form of ring. This ring oscillator’s output oscillates between the true and false stages controlled by applied voltage. Now days this voltage controlled oscillator (VCO) becomes the heart of modern electronic devices and communication systems. Earlier five-stage complementary metal oxide semiconductor (CMOS) based VCO for the Phase Locked Loop (PLL) was implemented. High frequency oscillations are required for many applications and further it is observed that a very general technique is normally adopted by researchers to achieve high frequency that if number of transistors is increased then the frequency can be increased. But the consequences of increase in number of transistors are the increase in delay and more number of MOSFET occupies more area and more power dissipation. So, in this paper VCO is designed with efficient utilization of MOSFETs. There is a balance between frequency and number of transistors, so that the area and power dissipation can be reduced. From the obtained results it can observed that the number of MOSFET’s, Independent Nodes, boundary nodes total nodes and power are reduced compared to five stage VCO and VCO based Ring oscillator.

Design and Application of Double-Gate MOSFET in Two Loops Controlled Multi-Input DC-DC Converter

Design and Application of Double-Gate MOSFET in Two Loops Controlled Multi-Input DC-DC Converter

A Noise Immune Double Suspended Gate MOSFET for Ultra Low-Power Applications

The purpose of this paper is to develop the design and analytical modelling of a noise immune double suspended gate MOSFET (DSG-MOSFET) for ultra-low power applications. Also, important performance parameters of the proposed structure such as pull-in and pull-out voltages have been thoroughly investigated with respect to the valuable structural parameters. The design methodology used is EKV based analytical approach to calculate the pull-in and pull-out voltages with ingeniously developed boundary conditions which helps achieving reasonably accurate result. Also, the I-V characteristics has been modelled to justify accuracy. The experimental result shows that the pull-in and pull-out voltages are in millivolts and microvolts range and hence it can be used in ultra-low power applications. As the ratio between the pull-out and the pull-in voltage is 10^(+3) range, justifies that the proposed structure is noise immune. The ID-VGS characteristic has hysteresis and this sharp transition in pull-in and pull-out voltage indicates that it can be used as an ideal switch with infinite sub-threshold slope. This paper presents a compact EKV based analytical modelling of pull-in and pull-out voltages for a DSG-MOFET which predict the device characteristics reasonably similar to simulated results. Also, for the first time the noise immunity for a DSGMOSFET has been analyzed.

Design and simulation of gallium nitride trench MOSFETs for applications with high lifetime demand

Design and simulation of gallium nitride trench MOSFETs for applications with high lifetime demand

(Invited) Crystalline Oxide Semiconductor Applicable to Low-Power Consumption Edge AI

Scaling of Si MOSFETs has proceeded based on scaling law reported by R. H. Dennard in 1974[1], and technologies scaled down to 5 nm node are currently incorporated in ICs in production. Meanwhile, according to an IEEE semiconductor roadmap[2], the 5-nm node device has a gate length of 18 nm, suggesting that scaling is reaching its limit.FETs using crystalline oxide semiconductor (OS), especially, c-axis-aligned crystalline (CAAC)-IGZO, are highly compatible with BEOL process of CMOS because OSFETs can be fabricated at 450°C or lower. Unlike bulk Si, OSFETs can adopt a trench-gate-self-aligned (TGSA) structure[3] enabling isolation from the substrate and accommodating chip bonding technologies. Crystalline oxide semiconductor process contributes to vertical integration required in the future technology.FETs using CAAC-IGZO is preferred to have a charge accumulation structure such as n-i(n-)-n junction (FIG. 1) in which its channel region, especially the region direct below the gate, has to be adjusted to have an i(n-)-type conductivity. Such a junction structure enables threshold voltage control and a reduction in leakage current of the FET. The leakage current of the CAAC-IGZO FET is extremely low, yA (10-24 A)/mm measured at the transistor level at 85°C, which is lower by 10 digits than that of a CMOS device[3].A variety of applications using crystalline OS have been studied, including AI accelerators, high-resolution displays, nonvolatile memories and combination with sensors. Among them, an AI accelerator using crystalline OS has attracted attention[4]. Using crystalline OS enables memory to be placed near compute units. It can also be driven with low current; accordingly, improvement in computational efficiency is expected.Crystalline oxide semiconductor process is a promising technology enabling both high integration and lower power consumption of ICs with CMOS devices. ＜ Reference ＞ [1] R. H. Dennard et al., “Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions,” IEEE Journal of Solid-State Circuits, vol 9, Issue 5, pp.256-268, 1974.[2] International Roadmap for Devices and Systems (IRDS™) 2020 Edition, 2020.[3] H. Kunitake et al., “A c -Axis-Aligned Crystalline In-Ga-Zn Oxide FET With a Gate Length of 21 nm Suitable for Memory Applications,” IEEE J-EDS, vol. 7, pp. 495-502, 2019. Yamazaki et al., “Crystalline IGZO ceramics (crystalline oxide semiconductor)–based devices for artificial intelligence,” Ceramic Engineering & Science, vol. 1, Issue 1, pp.6-20, 2019. [4] D. Saito et al., “IGZO-Based Compute Cell for Analog In-Memory Computing—DTCO Analysis to Enable Ultralow-Power AI at Edge,” IEEE Transactions on Electron Devices, vol. 67, Issue 11, pp.4616-4620, 2020.FIG. 1: Electron holography analysis result of sample using crystalline OS. Figure 1

Implementation of Low Voltage MOSFET and Power LDMOS on InGaAs

In this paper, a new low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) have been proposed with concept of integration based on trench technology on InGaAs material. Junction isolation technique is used for the implementation of a low voltage MOSFET and a high power dual gate MOSFET in same InGaAs epitaxial layer side by side. The HV DG MOSFET consists of dual gate that are placed in drift region under the oxide-filled trenches. The proposed structure minimize on-resistance (Ron) along with increased breakdown voltage (Vbr) due to enhanced RESURF effect, the creation of dual channels, and due to folding technique of drift region in vertical direction. In the HV DG MOSFET, the drain current (ID) increases leading to enhanced transconductance (gm) by simultaneous conduction of channels with improved maximum oscillation frequency (fmax) and cut-off frequency (ft). On the other side, the low voltage MOSFET consists of a gate placed in a centre of the structure within an oxide trench to create two n-channels in the p-base. The two channels are conducting in parallel and give substantial enhancement in peak gm, ID, fmax and ft with more control over the short channel parameters. The design and performance analysis of low voltage MOSFET (LV MOSFET) and high voltage dual-gate MOSFET (HV DG MOSFET) are carried out on 2-D ATLAS device simulator.

Short-Channel Effects in SiC MOSFETs Based on Analyses of Saturation Drain Current

In this brief, the minimum channel length (the channel length at which short-channel effects (SCEs) begin to occur) in SiC MOSFETs was experimentally determined. We fabricated 4H-SiC MOSFETs with various channel lengths and acceptor concentrations and analyzed their electrical characteristics. We propose a method for determining the minimum channel length in silicon carbide (SiC) MOSFETs, focusing on the increased rate of the drain current in the saturation region, and define the minimum channel length for the fabricated SiC MOSFETs with various acceptor concentrations in the p-body region. The relationship between the minimum channel length and the acceptor concentration for these SiC MOSFETs shows a similar tendency to that for Si MOSFETs. The obtained minimum channel lengths in the SiC MOSFETs are slightly longer than those in Si MOSFETs, which is caused by the larger built-in potential of SiC compared to that of Si and the existence of a high density of interface states, which enhance the SCEs. This work provides guidelines for the design of SiC MOSFETs that utilize very short-channel structures.

Capacitive Modeling of Cylindrical Surrounding Double-Gate MOSFETs for Hybrid RF Applications

The advancements in semiconductor technology greatly impact the growth of hybrid VLSI devices and components. The nanometer technology has been possibly executed due to the enhancement of the scaling factor of the MOSFETs. Since the MOSFETs play a vital role in building dense devices, it also has several research insights with various semiconductor materials with high-κ dielectrics. The high-κ dielectric material in place of the conventional oxide layer in the MOSFET design results in improved performance by reducing the Short Channel Effects (SCEs). In this research work, an analytical model of the lightly doped Cylindrical Surrounding Double-Gate (CSDG) MOSFET has been realized. The capacitive modeling has been done for this cylindrical structure. This modeling has been analyzed for all operating regions of the transistors, capacitance estimation, and electrical field dependence on the capacitance. The results have been compared with the previous research and tabulated. It has been observed that the transconductance (G <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sub> ) values have been raised to 0.0106 S/μm from 0.000645 S/μm with the inclusion of 2D electron gas in the core of CSDG MOSFET. This novel model occupies less area on the board, and routing is more accessible than the conventional DG MOSFET design. The overall results have been following the agreement in terms of accuracy, area tradeoff, and high speed, making the novel model suitable for high-frequency/RF applications.

2-D Design of Double Gate Schottky Tunnel MOSFET for High-Performance Use in Analog/RF Applications

In this work, a new structure of Schottky tunneling MOSFET has been designed and simulated. The proposed device structure uses floating gates and dual material main gates to counter short channel effects and to improve RF/Analog figures of merit for low power design applications. The use of floating gates modulates the Schottky barrier width, hence improves the ON state and RF/Analog figures of merit performance of the proposed device in comparison to a conventional device. A significantly high I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ( 1.231×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4 </sup> A/μm) and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio ( 2.52×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ) is achieved in the proposed ST-MOSFET in comparison to conventional ST-MOSFET having I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON </sub> (1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-7</sup> A/μm) and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio ( 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ). It has been observed that there is more than 100 times improvement in cutoff frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ), transconductance frequency product (TFP), gain frequency product (GFP), gain transconductance frequency product (GTFP), gain bandwidth product (GBP) and max oscillation frequency ( f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> ) in comparison to conventional ST-MOSFET. In addition, there are reductions of 98% and 33.33% in switching ON and OFF delays respectively in the proposed device-based inverter circuit in comparison to conventional ST-MOSFET based inverter circuit. Furthermore, the proposed ST-MOSFET device does not require any highly doped regions, hence does not have any doping related issues.

Junction Design and Complementary Capacitance Matching for NCFET CMOS Logic

Negative capacitance field effect transistors (NCFETs) are modeled in this study, with an emphasis on junction design, implications of complementary logic, and device V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> menu enablement. Contrary to conventional MOSFET design, increased junction overlap is beneficial to NCFETs, provided the remnant polarization ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">r</sub> ) is high enough. Combining broad junctions with complementary capacitance matching (CCM) in MFMIS (metal/ferroelectric/metal/insulator/semiconductor) NCFETs, it is shown that super-steep and non-hysteretic switching are not mutually exclusive, and that it is theoretically possible to achieve non-hysteretic sub-5 mV/dec SS over >6 decades. In a CMOS circuit, due to CCM, low- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> pairs provide steeper subthreshold swing (SS) than high- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> pairs. Transient power/performance is also modeled, and it is shown that a DC-optimal NCFET design, employing broad junctions, CCM, and a low- V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> NFET/PFET pair, does not translate to improved AC power/performance in unloaded circuits compared to a conventional FET reference. It is also shown that the same non-hysteretic DC design point is hysteretic in AC and may also lead to full polarization switching at higher voltages. Thus, a usable voltage window for AC NCFET operation forces a retreat from the DC-optimal design point.

Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage ( V TH1 ) could be reduced compared to the external gate ( V TH2 ) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs).

Design and Fabrication of 4H-Sic Mosfets with Optimized JFET and p-Body Design

In this paper, 4H-SiC planar MOSFETs were designed and fabricated. By using TCAD tool, the trade-off between on-resistance and maximum gate oxide electric field was optimized. With optimized gate oxide growth process, the gate oxide’s critical electric field of 9.8 MV/cm and the effective barrier height of 2.57 eV between SiO2 and 4H-SiC were obtained. The field effective mobility with different p-body doping was compared and studied. The MOS interface state density of 1.12E12 cm-2eV-1 at EC - EIT = 0.21 eV and channel mobility of 19.3 cm2/Vs at VGS = 20 V were obtained. The fabricated MOSFET’s on-resistance of 6.4 mΩcm2 was obtained with hexagonal cell structure which is very consistent with the simulation results.

The Transistor, an Emerging Invention: Bell Labs as a Systems Integrator Rather Than a ‘House of Magic’

The transistor is one of the most consequential human inventions with dissemination of the eventual MOS-FET design estimated to exceed one quintillion devices. However, the transistor’s genesis remains poorly understood. Many received accounts associate transistor invention closely with a small group of Bell Labs scientists during the 1947-1948 period. This paper argues that such a view is too narrow. Rather, the transistor – as a solid-state amplifier – emerged over a period of several decades starting with early observations of anomalous amplification in semiconductor crystals and early device designs during the 1910s and 1920s. Other types of relevant knowledge evolved in the form of advances in solid-state physics and materials processing techniques during the 1930s and early 1940s. Bell Labs identified, absorbed, evaluated, and integrated such diverse but interrelated knowledge streams – making Bell Labs appear much more like a systems integrator than the prototypical closed innovation organization it is often portrayed as. The Bell Labs transistor effort was both mission- and device-oriented with the specific goal of turning existing but imperfect solid-state amplifier designs into reliable substitutes for vacuum tubes – as such the research program is better described as applied industrial research rather than basic research. Through its systems integration activities, Bell Labs catalyzed a qualitative shift in the hitherto fragmented semiconductor field, enabling greater resource allocation and intensified research activity, as reflected in a hike in publication growth rates and the later introduction of marketed products. Thus expanded research activity eventually led to the 1959 MOS-FET design as the transistor’s dominant design used in large-scale dissemination such as in modern computer chips. Consequently, I propose to view the transistor as an emerging invention – in contrast to a discrete or singular one – with an emergence period spanning several decades. I propose to distinguish between an exploration phase (~1920-1945), a consolidation phase (1945-1950), and a maturation phase (1950-) whereas the intermediate consolidation phase represents a topological transition as is characteristic of emerging fields. Another emphasis of this article lies on the role of informal knowledge in the invention process. In the transistor case, such informal knowledge included patent specifications with proposed device designs, amateur radio magazine articles with reported anomalies, and oral anecdotes in practitioner circles describing experimental configurations of interest. This research asserts that such kinds of informal knowledge played an important role early on in the invention process as they guided both early research campaigns and managerial decisions, including at Bell Labs.

Investigation and design of ion-implanted MOSFET based on (18 nm) channel length

The aim of this study is to invistgate the characteristics of Si-MOSFET with 18 nm length of ion implemented channel. Technology computer aided design (TCAD) tool from Silvaco was used to simulate the MOSFET’s designed structure in this research. The results indicate that the MOSFET with 18 nm channel length has cut-off frequency of 548 GHz and transconductance of 967 μS, which are the most important factors in calculating the efficiency and improving the performance of the device. Also, it has threshold voltage of (-0.17 V) in addition obtaining a relatively small DIBL (55.11 mV/V). The subthreshold slope was in high value of 307.5 mV/dec. and this is one of the undesirable factors for the device results by short channel effect, but it does not reduce its performance and efficiency in general.