Low-power Design Research Articles

Review of innovations in low-power flip-flops based on the development of innovative logic gates

Integrated circuits have advanced quickly alongside the semiconductor industry's tremendous growth. The primary design considerations for each circuit in a VLSI data path are minimization of area and power consumption. As a very important logic unit in the integrated circuit, reducing the flip-flop's power consumption is of great significance for improving the performance of the whole circuit. There are many ways to reduce the power consumption of the flip-flop. This paper reviews several new low-power flip-flop designs using methods to improve the logic structure of flip-flops and their logic gates, including a reversible flip-flop design with reversible gates, a flip-flop design with memristors, and a sense amplifier-based flip-flop. The analysis shows that all three options for improving the logic gate can reduce the power consumption of the flip-flops and also have a positive effect on reducing the size of the device.

THE DESIGN OF HIGH EFFICIENCY AND LOW POWER SWITCHED OPAMP

The tendency of design of integrated circuits (ICs) goes to through the power and area reduction way. The surface area of very-large scale integrated circuits is shrinking along with the shrinking of technological dimensions. Power reduction requires usage of low-power design methodologies. The design of Switched-Opamp (SwOp) circuit based on typical Operational Transconductance Amplifier (OTA), with high efficiency is presented. Reduction of power consumption, using digitally controlled switches, is provided. The suggested SwOp was fabricated in a 14nm FinFET technology and achieved a DC gain of 38.4dB, a maximum operating frequency of 11.5GHz and a power consumption of 114.48uW for worst corner (SS) when the load capacitor is 5pF. The power consumption of proposed architecture is reduced about two times. Structure proposed in the paper can be integrated in modern analog-to-digital conversion application, high-speed receivers, memory systems.

A Low-Power V-Band Radar Transceiver Front-End Chip Using 1.5 V Supply in 130-nm SiGe BiCMOS

Energy-efficient, low-voltage, and low-power millimeter-wave (mm-wave) radars are gaining increasing attention for battery-powered commercial applications. In this article, the design of a low-power <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> -band radar sensor based on a transceiver (TRX) front-end chip using 1.5 V supply in an advanced SiGe BiCMOS technology with 300 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{f}\textsubscript{T}$</tex-math> </inline-formula> and 500 GHz <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{f}\textsubscript{max}$</tex-math> </inline-formula> is presented. The monostatic front-end chip utilizes low-voltage low-power circuit-level design techniques to achieve measured 9-dBm transmitter (TX) output power and 27-dB receiver (RX) gain with a simulated 3.8-dB noise figure (NF) consuming a total of only 72 mW in continuous mode. The TRX chip is used to build a radar sensor, which is experimentally verified in an anechoic chamber. The low-power sensor achieves a 46-dB dynamic range and a ranging precision better than 3.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m measured with a static target at 1 m. Phase measurements using the low-power radar in the continuous-wave (CW) mode demonstrate that submillimeter movements can be tracked, and notably main vital parameters of a human can be determined accurately. Experimental results show that the performance of the proposed low-power TRX front-end chip is very competitive with designs in modern CMOS technologies.

A robust low-power fsm cordic lms filter design for exponential noise removal in pacemaker

ABSTRACT Heart disease is identified to be the major reason for death worldwide as recorded by World Health Organization. The use of cardiac pacemakers was estimated to be around 1.14 million in the year 2016 and is expected to increase to 1.43 million by the year 2023. Based on the frequency of usage, the lifetime of a pacemaker can last between 6 to 10 years. To prolong the lifetime of the pacemaker, a low-power filter design is presented. The pulse that comes out of the pacemaker has exponential noise and myo-potential noise. The least mean square (LMS) filter with Co-ordinate Rotation Digital Computer (CORDIC) filters the exponential noise signal and retrieves the desired pace pulse. The CORDIC architecture used here is realised using FSM computational technique, because FSM offers a simple hardware circuitry. Digital circuits highly rely on clock signal to track the time and execution of functions that are programmed. This irreplaceable signal requires a control module that would make it more efficient and audacious. This is the prime reason for the evolution of clock gating technique. Similarly, the leakage power caused by the power source also requires attention. With the boom of deep submicron technologies, leakage power has started to occupy 30–50% of the total power consumption. Power gating technique helps to resolve this issue significantly. In this proposed method, integrated coarse-grained power and clock gating technique is employed to reduce the power dissipation of the LMS filter. A comparative study of Latch-, AND- and OR-based clock gating with forced transistor stacking and sleep transistor whose width and length are doubled from the rest of the complementary metal oxide semiconductors is also performed. The design is implemented using 250 nm CMOS technology. The implementation of clock gating technique has resulted in a 41.35% average reduction in dynamic clock power dissipation. The power gating technique has resulted in 26.08% reduction in static input power dissipation. The total power savings on integration of clock and power gating techniques are found to be 36.95% from the non-gated CORDIC LMS filter design.

SkyBridge 2.0: A Fine-grained Vertical 3D-IC Technology for Future ICs

Gate-all-around field effect transistors (FETs) are set to replace FinFETs to enable continued miniaturization of ICs in the deep nanometer regime. IMEC and IRDS roadmaps project that 3D integration of gate-all-around FETs is a key path for the IC industry beyond 2024. In this article, we present SkyBridge 2.0, an IC technology featuring high density fine-grained 3D integration of vertical gate-all-around nanowire FETs, contacts, and interconnect while also solving 3D routability. We utilize industry-standard EDA tools to develop a customized design and technology co-optimization (DTCO) flow to design and evaluate SkyBridge 2.0. This DTCO flow covers process emulation of standard cells and SRAM to enable scalable manufacturing pathway, TCAD characterization of vertical nanowire FETs to obtain IV and CV characteristics, compact modeling accurately the device behavior, RC parasitic extraction of 3D interconnects and performance, and power and area assessment using ring oscillators. The technology assessment using ring oscillators shows that SkyBridge 2.0 at the chosen design point, using 10 nm nanowires, achieves ∼18% performance and 31% energy efficiency benefits compared to 7 nm FinFET technology. Area analysis of logic cells shows up to six times density benefits versus aggressively scaled 2D-CMOS cells. In addition to logic, we architect 3D SRAM to support low-power memory designs. SkyBridge 2.0 SRAM shows ∼20% improvement in read and write static noise margin, up to three times lower leakage current, and up to four times density benefits compared to 7 nm FinFET technology.

A Hybrid CMOS Digital-to-Analogue Converters Design for High Resolution SAR ADC

The paper describes the design and implementation of a 14-bit differential Digital-to-Analogue Converter (DAC) based on the Silterra 0.18µm Complementary Metal-Oxide-Semiconductor (CMOS) process to be established in a Successive Approximation Register (SAR) Analogue-to-Digital Converter (ADC) for the purpose of high-resolution, high accuracy and low power applications. The proposed differential DAC aims to eliminate the issue of stringent matching requirements imposed on high-resolution DACs while leveraging both linearity performance and power consumption parameters at a balanced point. The overall differential circuit consists of two parallel single-ended DACs that utilize a 4-bit Capacitor DAC (CDAC) and 10-bit Resistor DAC (RDAC) on each end, thereby establishing a hybrid-based architecture. Furthermore, the authors illustrate the proposed switching procedures applied to the sub-DAC circuits to ensure a low-power design is established. The new method effectiveness evaluation is confirmed by detailed transient simulations implemented on the DAC where the circuit performs the required conversions at a maximum conversion frequency of 2.5 MS/s with a peak power consumption of 0.1496mW for the standard voltage supply of 2.1V. Meanwhile, the schematic and post-layout simulations performed on the DAC registers peak DNL errors of -0.1612 and -0.8272, respectively. New research results depict performance improvements in terms of resolution and power consumption which facilitates the DAC implementation in contemporary electronic devices such as microcontroller peripherals and audio amplification devices. The overall deigned circuit is capable of achieving the desired 14-bit digital-to-analogue conversions under the CMOS 0.18µm technology, proving the DAC’s high-resolution efficacy.

CNTFET and RRAM Based Low Power Design of Unbalanced Ternary Logic Gates and Arithmetic Circuits

The advent of multi-valued logic (MVL) systems provides considerable improvements in energy consumption and computational efficiency compared to binary logic systems. Using resistive random-access memory (RRAM) and carbon nanotube field effect transistors (CNTFETs), this manuscript presents a new design method for ternary logic gates (standard ternary inverter (STI), ternary NOR, and ternary NAND) and some arithmetic circuit applications are implemented based on the proposed ternary logic gates. The simulations of the proposed circuits are carried out in Synopsis HSPICE software by employing 32-nm Stanford CNTFET technology along with the Stanford RRAM model. The robustness of the designed CNTFET-RRAM STI circuit is investigated for variations in process parameters. Simulation results verify that the proposed designs outperform other CNTFET based ternary logic circuits in terms of number of components, power consumption, delay and power delay product (PDP). Furthermore, a reduced change is perceived with respect to power consumption and PDP of the presented logic gates with process deviation, and variations in supply voltage, temperature, capacitance and frequency. The presented STI, TNAND, TNOR, ternary half adder (THA) and ternary multiplier (TMUL) circuits exhibit an improvement in PDP with less transistor count as compared to the other existing designs in the literature.

Dielectrically modulated ferroelectric-TFET (Ferro-TFET) based biosensors

The study discovers the biosensing analysis of Ferro-TFET. The biosensor developed is based on the dielectric modulation technique. Besides the incorporation of nano-cavities close to both the source and drain region results in the increased capture area. Ferro-TFET biosensor is analyzed for performance parameters such as threshold voltage (SVTH), ON-OFF current ratio (SION/IOFF), and drain current (SId) sensitivity. The characterization is done for biomolecules considering charge to be neutral, positive, and negative for different values of dielectric constants between the immobilization layer and insulator interface. Also, an exhaustive evaluation is done for the case when nano-cavities are partially filled which initiates due to the steric hindrance and is found to be conferred with the real-time situation. The work investigated nano-cavities considering partially filled for the arrangement of biomolecules in nature of distribution similar to convex, concave, increasing, and decreasing configuration in addition to the situation of biomolecules placed in nanocavities an asymmetric distribution. In the work, different sensitivity parameters of Ferro-TFET are compared with the state-of-the-art biosensors presented in the literature to establish the efficiency of the proposed biosensor. The Ferro-TFET biosensor improves the performance in comparison to conventional TFET-based biosensors as ferroelectric material when used as oxide material improves the subthreshold swing, improves the gate control over the channel, and establishes its applicability in low-power biosensor design.

Low-power wireless sensor design for LoRa-based distributed energy harvesting system

With the development of electronic power technology, distributed clean energy harvesting is widely concerned, in the process of distributed energy harvesting, the process of monitoring energy harvesting equipment does not need to transmit a large amount of data to the host device, a small amount of status information can meet the purpose of monitoring, so in the wireless sensor network energy consumption is an important issue to be considered. It is very energy efficient, can transmit wireless data over long distances, and supports mesh networking. In the process of distributed energy harvesting, the wireless sensor network composed of LoRa can effectively monitor the environmental information and wireless energy harvesting system, and the battery requirement is very low, and the data can be distributed with very little power consumption, which can be used in harsh environment and remote mountainous areas. In this paper, the composition of the distributed energy harvesting system is discussed first, then the energy situation of LoRa in low-power wireless energy transmission is analyzed, and finally the wireless low-power sensor network is tested.

Design of reverse converters for the general RNS 3-moduli set {2k, 2n − 1, 2n + 1}

This paper presents a new design method of the reverse (residue-to-binary) converter for the flexible 3-moduli residue number system (RNS) set { 2^k, 2^n-1, 2^n+1 }, where k and n are a pair of arbitrary integers ge 2. The basic equation of the reverse converter is formulated in two alternative forms, each of which consists of two separate parts: one depending on input variables of the converter, and the other being a single constant. The constant can be either added inside the reverse converter or shifted out to the residue datapath channels, in most cases at no hardware cost or extra delay. From the set of basic functions, which are essentially different than those of the only two known general converters proposed for this moduli set, four versions of a converter can be designed for any pair of k and n. Experimental results obtained using the commercial 65-nm low-power design kit and industrial synthesis tools for all dynamic ranges from 8 to 40 bits suggest that, compared to the state-of-the-art designs, at least one version of the newly proposed converters is superior w.r.t. delay, power consumption, and area, for all dynamic ranges considered. The savings for the best versions (these with constants moved to the datapath channels) are up to 12.7% for the area and from 2.5% to 14% (5.8 % on average) for the delay, while the power consumption is reduced up to 23.2% (5.6% on average).

Low-cost, low-power, clockwork syringe pump

A low-cost ($120 NZD, $75 USD), low-power (1-year battery life), portable, and programmable syringe pump design is presented, which offers an alternative to high-cost commercial devices with limited battery life. Contrary to typical motor-driven syringe pumps, the design utilizes a compression spring coupled with a clockwork escapement mechanism to advance the syringe plunger. Full control over flow-rate and discrete (bolus) deliveries is achieved through actuation of a clockwork escapement using programmable, low-power electronics. The escapement mechanism allows the syringe plunger to advance a fixed linear distance, delivering a dose size of 0.001ml in the configuration presented. The modular pump assembly is easily reconfigured for different applications by interchanging components to alter the minimum dose size. Testing to IEC 60601-2-24(2012), the average error of the clockwork syringe pump was 8.0%, 4.0%, and 1.9% for 0.001ml, 0.002ml, and 0.01ml volumes, respectively. An overall mean error of 1.0% was recorded for a flow-rate of 0.01mlh−1. Compared to a commercial insulin pump, the clockwork pump demonstrated reduced variability but greater average error due to consistent over-delivery. Further development of the design and/or manufacture should yield a device with similar performance to a commercial pump.

Wide-range and area-selective threshold voltage tunability in ultrathin indium oxide transistors

The scaling of transistors with thinner channel thicknesses has led to a surge in research on two-dimensional (2D) and quasi-2D semiconductors. However, modulating the threshold voltage (VT) in ultrathin transistors is challenging, as traditional doping methods are not readily applicable. In this work, we introduce a optical-thermal method, combining ultraviolet (UV) illumination and oxygen annealing, to achieve broad-range VT tunability in ultrathin In2O3. This method can achieve both positive and negative VT tuning and is reversible. The modulation of sheet carrier density, which corresponds to VT shift, is comparable to that obtained using other doping and capacitive charging techniques in other ultrathin transistors, including 2D semiconductors. With the controllability of VT, we successfully demonstrate the realization of depletion-load inverter and multi-state logic devices, as well as wafer-scale VT modulation via an automated laser system, showcasing its potential for low-power circuit design and non-von Neumann computing applications.

Securing AES Designs Against Power Analysis Attacks: A Survey

With the advent of Internet of Things (IoT), the call for hardware security has been seriously demanding due to the risks of side-channel attacks from adversaries. Advanced Encryption Standard (AES) is the de facto security standard for such applications and needs to ensure a low power, low area and moderate throughput design apart from providing high security to these devices. Substitution-box (S-box), being the core component of AES, has always drawn the attention of the cryptographic community. A chronological development of the S-box over a period of 20-years since the inception of AES is presented. This paper provides the first comprehensive review of the state-of-the-art S-box design techniques, identifying current advancements and analysing their impact on gate count, area, maximum frequency of operation, throughput and power. The other goal of the survey is to study the countermeasures designed for AES to protect it against side-channel attacks. In particular, we consider the power analysis attacks, and the countermeasures are investigated in terms of their security metrics and design overheads, such as area, power, and performance. The countermeasures are based on hiding or masking approaches depending on their design principle. Similar to the S-box survey, a chronological development of the countermeasures since the discovery of power analysis attacks in 1999, is presented. Finally, we suggest some open research gaps and possible direction of research in terms of S-box and countermeasure designs.

Energy Prediction Models and Distributed Analysis of the Grinding Process of Sustainable Manufacturing.

Grinding is a critical surface-finishing process in the manufacturing industry. One of the challenging problems is that the specific grinding energy is greater than in ordinary procedures, while energy efficiency is lower. However, an integrated energy model and analysis of energy distribution during grinding is still lacking. To bridge this gap, the grinding time history is first built to describe the cyclic movement during air-cuttings, feedings, and cuttings. Steady and transient power features during high-speed rotations along the spindle and repeated intermittent feeding movements along the x-, y-, and z-axes are also analysed. Energy prediction models, which include specific movement stages such as cutting-in, stable cutting, and cutting-out along the spindle, as well as infeed and turning along the three infeed axes, are then established. To investigate model parameters, 10 experimental groups were analysed using the Gauss-Newton gradient method. Four testing trials demonstrate that the accuracy of the suggested model is acceptable, with errors of 5%. Energy efficiency and energy distributions for various components and motion stages are also analysed. Low-power chip design, lightweight worktable utilization, and minimal lubricant quantities are advised. Furthermore, it is an excellent choice for optimizing grinding parameters in current equipment.

Low-Power Reconfigurable FIR Filter Design Based on Common Operation Sharing

This paper presents a low-power, fully reconfigurable finite impulse response (FIR) filter structure based on common operation sharing. Different from existing multiplexer(MUX)-based designs, the decoding of coefficients and compensation of negative-coefficient errors, which are the common operations for all the taps, are implemented by shared modules to reduce the overall hardware complexity. To validate the proposed structure, a proof-of-concept reconfigurable FIR filter is implemented and fabricated using 40 nm CMOS technology. Chip measurement results show that the proposed design is superior to existing methods in area-delay product and power performance, making it suitable for low-power filtering applications. The idea of sharing common operations for all taps can benefit the existing MUX-based filter techniques for further improvement of power and circuit complexity.

A low-power SRAM design with enhanced stability and ION/IOFF ratio in FinFET technology for wearable device applications

ABSTRACT Wearable device applications such as smartwatches, fitness trackers, and health monitors rely on batteries for power and require static random-access memory (SRAM) with low power consumption and high stability to ensure accurate sensor readings during prolonged operation. In this regard, this paper proposes a novel low-power single-ended 10-transistor (SE10T) SRAM cell with high stabilities. It utilises a stacked pull-down structure for hold/read stability improvement and leakage power reduction, a feedback-cutting mechanism for writability enhancement, and single-ended read/write structures for dynamic power reduction. Also, using a single-transistor reading path with eliminated read bitline leakage enhances ON-to-OFF currents (I ON /I OFF ) ratio. The proposed design is compared with the conventional 6T, Schmitt-trigger 10T (ST10T), differential writing 10T (DW10T), data-independent read port 10T (DIRP10T), transmission gate read-decoupled 9T (TGRD9T), and feedback-cutting 11T (FC11T) SRAM cells based on 7-nm Fin-shaped Field-Effect Transistor (FinFET) technology at V DD = 0.4 V. The proposed design shows at least 1.04×/1.01×/1.12×/1.25×/1.15× improvement in read stability/writability/read delay/leakage power/dynamic power. Moreover, it shows at least 1.22× improvement in I ON /I OFF ratio and offers the lowest minimum operating voltage (0.292 V). However, it offers a 1.02× lower hold stability than that of ST10T, a 1.18×/1.14×/1.13× higher write delay compared to 6T/ST10T/DW10T, and a 1.56×/1.07×/1.05× higher layout area occupation in comparison with 6T/TGRD9T/DIRP10T. Therefore, the proposed SRAM cell can be an optimum candidate for usage in smartwatches.

A Compact and Low-Power SoC Design for Spiking Neural Network Based on Current Multiplier Charge Injector Synapse.

This paper presents a compact analog system-on-chip (SoC) implementation of a spiking neural network (SNN) for low-power Internet of Things (IoT) applications. The low-power implementation of an SNN SoC requires the optimization of not only the SNN model but also the architecture and circuit designs. In this work, the SNN has been constituted from the analog neuron and synaptic circuits, which are designed to optimize both the chip area and power consumption. The proposed synapse circuit is based on a current multiplier charge injector (CMCI) circuit, which can significantly reduce power consumption and chip area compared with the previous work while allowing for design scalability for higher resolutions. The proposed neuron circuit employs an asynchronous structure, which makes it highly sensitive to input synaptic currents and enables it to achieve higher energy efficiency. To compare the performance of the proposed SoC in its area and power consumption, we implemented a digital SoC for the same SNN model in FPGA. The proposed SNN chip, when trained using the MNIST dataset, achieves a classification accuracy of 96.56%. The presented SNN chip has been implemented using a 65 nm CMOS process for fabrication. The entire chip occupies 0.96 mm2 and consumes an average power of 530 μW, which is 200 times lower than its digital counterpart.

A Dual-Mode Step-Down Converter with Automatic Mode Switch Circuit for System-on-Chip Applications

In this paper, a dual-mode step-down DC-DC converter with an automatic mode-switching circuit is implemented in a 28 nm digital CMOS process and embedded in an RF transceiver chip to power the digital part. The proposed automatic mode-switching circuit includes a frequency-voltage conversion circuit that is designed according to the principle of charge redistribution on capacitance. The converter can switch modes according to the load without external intervention. This converter, along with a PMU sequencer, can also provide a solution for low-power design for system-on-chip applications. The IC occupies a total die area of 0.378 mm2. The input voltage of the converter is 3.3 V, the output voltage is 1.05 V, and the maximum load current can reach 1 A. The converter shows a conversion efficiency of not less than 81% at a full load range and can achieve a peak conversion efficiency of 91% when the load current is 100 mA. The load range of the PWM mode is 1 A to 50 mA, and that of the PFM mode is 100 mA to 1 mA. The combination of zero-crossing detection circuitry and freewheel switches can reduce energy loss and eliminate additional electromagnetic interference.

Flexible FPGA 1D DCT hardware architecture for HEVC

In this work, we propose a flexible 1D DCT hardware design with a constant throughput of 32 pixels per cycle for all transform block (TB) size modes. The design supports all TB sizes defined in the HEVC standard. Flexibility is achieved by multiplexing only the outputs, which results in lower data path delays compared to other proposed designs. Also, the additional partial butterfly units are transferred to the output of transformation cores. The transformation operation is done in a single stage to minimize the latency of the design and reduce hardware usage. The highly parallel input reduces the need for a very high operational frequency, which is suitable for low-power FPGA designs. Four different reusable transformation cores are used that are designed using parallel Multiple Constant Multiplication (MCM) units to further reduce the calculation time. The design was implemented on the Virtex UltraScale + device. The implementation has hardware usage of 21,818 LUTs, and it can reach the maximal throughput of 4.90 Gsps at the working frequency of 153 MHz which is enough to support the video resolutions of up to 8192 × 4320@60fps. Comparison with the other works shows that DCT FPGA implementation without DSPs can reach the performance of the ASICs with trade-offs in power consumption.

Effects of logic glitch and (area-power dissipation) leakage on cryptosystems using clock gating technique to enhance web etiquette

The last century has seen an evolution in technology that has improved communication systems and, in general, made life easier for people. Our communication systems have become faster and more dependable as a result of the explosion of gadgets and services. But, these upgrades come at a price. The power consumption is one of the most worrying costs. In recent years, the solution involved installing larger, more powerful batteries—so long as doing so did not limit mobility. Today's economic and environmental problems compel us to consider alternative solutions, like methods for lowering the power consumption of digital devices. This study focuses on using digital circuits, which promise to deliver good energy efficiency and desirable performance at very low voltage savings. Certain digital switches are allegedly redundant and not required for the circuit to function properly, yet they continue to use energy. So, one of the primary issues for low power design is reducing such redundant switches. Subthreshold conduction in digital circuits is typically seen as a “parasitic” leakage in a condition where there should ideally be no conduction. Sub-threshold activities thereby reduce the problem of lowering power consumption, but do so at the expense of system throughput deterioration, fluctuations in system stability and functionality, temperature variations, and most critically, design space utilization. In order to minimize some of these redundant switches and to make circuits more energy-efficient while maintaining functionality, this study suggests two novel techniques. It uses an optimization method based on threshold voltage change to reduce glitch power. A glitch-free circuit netlist is created using an algorithm, while still maintaining the requisite delay performance. Using this approach results in a 6.14% overall reduction in energy consumption.