Design Of Logic Circuits Research Articles

Design and implementation of an inverter and its application in ring oscillator circuits using an organic-thin-film-transistor based on an FTM-derived channel

The organic thin film transistor (OTFT) has evolved in a big way, eventually replacing inorganic-based solid-state devices. An extensive survey of the literature reveals that the full potential of OTFTs has neither been explored nor exploited for circuit-level implementation for logic circuit design, despite the popularity of these devices. We have fabricated a PBTTT-C14 (poly (2,5-bis (3-tetradecylthiophen 2yl) thieno (3,2b) thiophene)) based OTFT by using a low-cost solution-processable technique via the floating transfer method (FTM). The fabricated OTFT using FTM shows better electrical behavior than its counterpart fabricated by using the conventional solution-processable technique. The superior electrical characteristics of the FTM-derived devices prompted us to develop a compact model of the p-channel OTFT. The compact modeling results of OTFT show a reasonably good agreement with our experimental results. We have also designed and implemented a PBTTT-C14 OTFT-based inverter circuit and ring oscillator circuit to explore the future of organic-based integrated circuits.

Design of low delay 4X4 SRAM memory using quantum dot cellular automation technology

Nanotechnology is concerned with materials, structures and systems whose components exhibit new and changing physical, chemical and biological properties as a result of their nanoscale sizes. It is a new technology used to design logic circuits with small size, low energy consumption and high frequency (of the order of Tera Hertz).and it is the leading candidate for the nanotechnology to replace the CMOS technologies that is used in manufacturing of the most today's electronic devices. In this research we have designed a low-delayed 4X4 SRAM circuit using the previous technology, The simulation results showed that the proposed design performs the required logic function with a delay that is about a third lower for the reading process and about a half for the writing process compared with the best previous designs of the same size or which allows reading/writing the same number of bits from/to memory.

Design of a new multiplexer structure based on a new fault-tolerant majority gate in quantum-dot cellular automata

Quantum-dot cellular automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement. The proposed gate consists of 11 cells and requires an area of 0.0096 μm2. The proposed design has 100% tolerance to the fault of a single missing cell and 71.43% tolerance to the rotation of one cell. The proposed 2-1 multiplexer consists of 41 cells and requires an area of 0.066 μm2. This multiplexer has 95.24% tolerance to the fault of a single missing cell.

Design and comparative analysis of memristor-based transistor-less combinational logic circuits

ABSTRACT Memristor-based combinational logic is one of the unique concepts of designing digital circuits to achieve compact design, faster operation, and lesser power consumption. This work presents a unique memristor-based transistor-less combinational logic circuits design and analyses the performance benchmarking with other state of the art methods. Observed results demonstrated that the proposed design performs comparatively well in terms of size, speed, and power consumption. Basic combinational logic circuits, such as full adder, multiplexer, decoder, and priority encoder are being designed using the University of Michigan Model. The basic logic gates which include AND, OR, XOR are also designed using the concept of memristor ratioed logic. The proposed design of full adder utilises 14 memristors and 2 inverters, the delay time is 26.5ps, and power consumption is 0.5nW which is less compared to the other design. The proposed 4 × 1 multiplexer, 2-to-4 decoder and 4-to-2 priority encoder consume 0.6nW, 0.15nW, and 0.87nW power respectively. The observed improvement in these significant parameters demonstrates the potential of using memristor-based transistor-less combinational logic circuits in modern electronic devices.

Design of New Over-Temperature Protection Light-Emitting Diode Driver Circuit and Improvement Method of Visual Design

The overall design of light-emitting diode (LED) display control system was completed at first. For the problems of LED driver chip such as low accuracy of constant current output, high power consumption, poor stability, and single over-temperature protection function, the double temperature hysteresis and over-temperature buffer protection function of circuit were designed. The low-power constant-current module of LED driver module included an operational amplifier, a MOS tube with negative feedback control, and the driving current required to achieve high-precision reference current conversion. The temperature control points were set in hysteretic and overtemperature buffer modules for the working temperature, and power MOS tube was turned off in time to reduce the driving current to a constant driving current, thus reducing the power consumption of circuit. In addition, to improve the image quality of LED display, a visual refresh logic circuit was designed. The display cycle was divided into 32 segments by logic circuit, with 128 gray clock cycles in each segment, and duty ratio was controlled by 12 bits of gray data. In test, the multi-value output bandgap reference voltage was simulated at first. In range of –30 °C–130 °C, the fluctuation of voltage in this temperature range met the requirements of circuit. During simulation of buffer circuit of the LED driver module, it was found that output terminal can perform good voltage following, so as to meet the needs of circuit. The design of visual refresh logic circuit can greatly improve the refresh rate of pulse width modulation (PWM).

Ultra-fast tunable optoelectronic half adder/subtractor based on photonic crystal ring resonators covered by graphene nanoshells

This paper reports a new design of a tunable optoelectronic half adder/subtractor. Two photonic crystal (PhC) ring resonators are used to realize the proposed structure. Several silicon rods surrounded by silica rods covered with graphene nanoshells (GNSs) form every PhC ring resonator. Setting the chemical potential of GNS with an appropriate gate voltage, we can tune the PhC resonant mode as desired. The plane wave expansion technique is used to study the photonic band structure of the fundamental PC microstructure, and the finite-difference time-domain method is employed in the final design for solving Maxwell's equations to analyze the light propagation inside the structure. We systematically study the effects of physical parameters on the transmission reflection and absorption spectra. By optimizing the geometric dimensions, resonant absorption peaks can be excited at the same time for GNSs. Our numerical results also reveal the maximum time response is about 0.8 ps. The 200 µm2 area of the proposed half adder/subtractor makes it the building block of every photonic integrated circuit. Also, the design of various fast signal processing systems in optical communication networks is possible due to using tunable GNSs in PhC ring resonators. This study can introduce the use of two-dimensional materials in the design and implementation of logic circuits.

Quantum-Dot Cellular Automata Based On Trainable Associative Memory Neural Network for Implementing Reconfigurable Logic Gates

CMOS technology has reached its physical scaling limits, power consumption limits, and hence CMOS technology has to be replaced by other emerging technologies. Quantum-Dot Cellular Automata (QCA) has proven to be a better solution since it offers better scaling and low power consumption for processing digital signals. However, due to a lack of optimization support improvements, dynamical QCA paradigms require multi-layer designs and increased computations. Hence in this paper, a reconfigurable logic gate based on QCA paradigms is proposed. The design utilizes training of memory cells associated with QCA paradigms and hence can be switched between AND, OR, and MUX logic circuit designs dynamically. Compared to traditional dynamical QCA, the model is designed on a single-layer substrate with a minimum number of cells and size.

Designing and Implementing a Fault-Tolerant Priority Encoder in QCA Nanotechnology

The quantum-dot cellular automata (QCA) is a new and impressive nano-technology for implementing electronic circuits at nanoscale. This nanotechnology is more impressive than CMOS technology in terms of higher speed, smaller area and less energy consumption, and can make significant progress in the design of logic circuits. quantum-dot cellular automata circuits are likely to have various defects during fabrication. In fabrication process, some different defects might be occurred (like cell deletion, cell addition, cell displacement, cell rotation, and misalignment). That’s why researchers are eager to design fault-tolerant circuits. In this paper, a fault-tolerant priority encoder is designed. For this purpose, a new fault tolerant majority gate is provided first. The results of simulations are shown with the QCADesigner software V2.0.3. The simulation results indicate an improvement in the performance of the proposed structure.

Differential Electrically Insulated Magnetoelectric Spin-Orbit Logic Circuits

Beyond complementary metal-oxide-semiconductor (CMOS) devices have functionalities different from CMOS transistors, and therefore, the development of novel circuits that leverage their properties is necessary for their practical application to computing. The magnetoelectric spin-orbit (MESO) device has been proposed as one of the promising energy-efficient beyond CMOS device candidates, and several basic circuit blocks have been demonstrated with MESO. In this work, we propose a new differential MESO device that enables differential logic circuit design with better interstage isolation. This improves the output voltage of MESO circuits, provides signal common-mode noise rejection, and eliminates any sneak current path. We demonstrate the functionality of multiple essential logic circuit blocks implemented with MESO devices.

DEVICE AND CIRCUIT LEVEL SIMULATION STUDY OF NOR GATE LOGIC FAMILIES DESIGNED USING NANO-MOSFETs

The investigation of silicon-based nano-MOSFETs logic circuits is helpful to gain more comprehensive knowledge about nanoscale transistors. Therefore, a simulation study has been performed on four logic families of two inputs NOR gate logic circuits, namely (i) nano-CMOS NOR gate, (ii) nano-MOSFET loaded n-type nano-MOSFET NOR gate, (iii) 733.8 Ω resistive loaded nano-MOSFET NOR gate, and finally (iv) pseudo-n-type nano-MOSFET NOR gate. The nano-MOSFET technology node studied in this paper is 10 nm. Device simulation is done using an online NanoMOS simulator, whereas circuit simulation is carried out using freeware WinSpice. The main obstacle encountered during downscaling of nano-MOSFETs is low power dissipation and high-speed nano-MOSFET logic circuits. Correct logical NOR operation has been proven by observing simulated timing waveforms. Transient timing analysis on nano-MOSFET loaded n-type nano-MOSFET NOR gate has shown that propagation delays calculated from theory and simulation are 66% matched. From the analysis, this 10 nm nano-MOSFET NOR logic circuit design exhibit a dynamic power reduction of 148 times and a propagation delay improvement of 33 times when benchmarked against a typical 120 nm MOSFET logic circuit.
 Keywords: nano transistor, electrical characteristics, channel length, channel width, benchmarking, power, speed

Optimal design for 1:2n demultiplexer using QCA nanotechnology with energy dissipation analysis

AbstractQuantum‐dot cellular automata (QCA) is an emerging technology to design logic circuits at the nanoscale level. It has the potential to replace the complementary metal oxide semiconductor (CMOS) technology. In this paper, an optimal, single layered, single clocked 1:2 demultiplexer (DeMux) circuit is proposed using 19 QCA cells in QCA technology. Proposed 1:2 DeMux circuit is further utilized for designing of 1:4 DeMux and 1:8 DeMux circuits using 72 and 206 QCA cells respectively. DeMux is an important module at the receiver side in the communication system. The performance of the proposed DeMux circuits are checked and compared with the available similar designs using QCA Designer‐E. Proposed 1:2 DeMux decreases 79.17% layout cost and 50% clock latency as compared to the best reported work in the literature. Proposed 1:4 DeMux reduces 48.57% cells count and 40.63% total area while proposed 1:8 DeMux cuts 63.54% cells count and 64.54% total area as compared to best reported similar works in the literature. Energy dissipation pays an important role to design the energy efficient circuits at nanoscale level. Energy dissipations are estimated using QCA Designer‐E and QCA Pro tools. Proposed 1:2 DeMux saves 8.20% total energy dissipation as compared to the existing design.

Design and Test of Digital Logic DNA Systems

This article describes DNAr-Logic, a software package that provides easy design and test of digital logic circuits in DNA computing without requiring in-depth knowledge of chemistry. -

Reconfigurable logic circuit design for stateful Boolean logic computing

Reconfigurable logic circuit design for stateful Boolean logic computing

Ultra low power design of multi-valued logic circuit for binary interfaces

From the dawn of the computer age, man has mass produced binary components for computers, due to which ternary or higher radix computers are not yet commercially used. It has been proved that ternary logic can be more efficient than binary logic and there are many devices in development that operate on more than two internal states. Therefore an efficient method to produce multi-valued logic on the basis of binary input provided is needed. In this article, an effective, simple, flexible, and low power consumption implementation has been proposed that can convert any binary number to a number of chosen radix. The proposed design is implemented in 32 nm TSMC CMOS. The proposed design is then evaluated in power/delay space and its performances are compared with the latest state of art designs. The proposed circuit exhibits power saving up to 92% over previous models.

An effective nano design of demultiplexer architecture based on coplanar quantum‐dot cellular automata

Quantum-dot cellular automata (QCA) are prospective nanotechnology with striking performance to tackle the shortcomings of complementary metal-oxide-semiconductor (CMOS) transistor-based technology such as fabrication dimensions and switching speed. The demultiplexer, as a crucial component for the design of many logic circuits, comprises a circuit for separating the multiplex data into the component data. The demultiplexer is highly utilised in the communication system for building serial data lines to parallel ones. So, its efficient schematisation has turned to an issue that has captured the concentration of the investigation group. Therefore, a novel structure of QCA-based one to two demultiplexers is proposed, and it is employed to design one to four demultiplexers. QCAdesigner software, as a powerful layout and tool for simulation, is utilised for evaluating the validity and practicality of the proposed structures. The detailed evaluation of proposed layouts shows excellent performance than prior operations, and notable developments regarding the occupied area, cell count, and latency.

Quantum image filtering and its reversible logic circuit design

Quantum image filtering and its reversible logic circuit design

Quantum image filtering and its reversible logic circuit design

Quantum information processing can overcome the limitations of classical computation. Consequently, image filtering using quantum computation has become a research hotspot. Here, a quantum algorithm is presented on the basis of the classical image filtering principle to detect and cancel the noise of an image. To this end, a quantum algorithm that completes the image filtering task is proposed and implemented. The novel enhanced quantum representation of digital images is introduced. Then, four basic modules, namely, position-shifting, parallel-CNOT, parallel-swap, and compare the max, are demonstrated. Two composite modules that can be utilised to realise the reversible logic circuit of the proposed quantum algorithm are designed on the basis of these basic modules. Simulation-based experimental results show the feasibility and the capabilities of the proposed quantum image filtering scheme. In addition, our proposal has outperformed its classical counterpart and other existing quantum image filtering schemes supported by detailed theoretical analysis of the computational complexity. Thus, it can potentially be used for highly efficient image filtering in a quantum computer age.

Theoretical Conditions for Field-Free Magnetization Switching Induced by Spin-Orbit Torque and Dzyaloshinskii–Moriya Interaction

Recently, it was demonstrated that field-free switching could be achieved by combining spin-orbit torque (SOT) and Dzyaloshinskii-Moriya interaction (DMI). However, this mechanism only occurs under certain conditions which have not been well discussed. In this letter, it is found that the ratio of domain wall width to diameter of nanodots could be utilized as a criteria for judging this mechanism. Influences of different magnetic parameters are studied, including exchange constant, DMI magnitude and field-like toque, etc. Besides, we reveal the importance of the shrinkage of magnetic domain wall surface energy for metastable states. Our work provides guidelines to the experiments on the DMI-induced field-free magnetization switching, and also offers a new way for the design of SOT-based memory or logic circuits.

The Design and Implementation of an Educational Augmented Reality Application for Logical Circuit Design

The purpose of the study is to determine the effect of augmented reality applications on the learning of engineering students in their professional courses. The objective of the study is to ensure that augmented reality technologies, which are among the most important technologies of today, are used in educational settings. The other important objective of the study is to ensure that the augmented reality technologies used in professional training in countries such as the USA, Canada and the Netherlands are also used in our country and to provide a world-class education opportunity. Also, contributing to the economy of our country with the successful studies to be carried out in this regard is among the objectives of the study because of the increasing interest in augmented reality software throughout the world and the formation of an important economy related to the development of these kinds of software.In the study, an augmented reality application developed by the researcher was used in the learning process of a subject included in the faculty of engineering education curriculum. The study was performed using a convergent parallel mixed-methods design in which both qualitative and quantitative data were used simultaneously. The result of the study showed that there were no significant difference between the average attitude towards AR applications of the students participating in the study and the gender, class, and father education level; however, it is seen that there was a significant difference between maternal education status. It was also determined that the difference between the students’ average attitude towards AR applications before and after the study was significant.Similarly, it was observed that the difference between the AR attitude averages before and after the study and the AG attitude average 4 weeks after the study was also observed to be significant. It was also found that the students who participated in the study found the AR applications remarkable, entertaining, understandable and useful for the instructor. Moreover, they stated that using AR applications in lessons would contribute to fast and active learning and increase success.

MoS2-on-AlN Enables High-Performance MoS2 Field-Effect Transistors through Strain Engineering.

Molybdenum disulfide (MoS2) has substantial application prospects in the field of electronic devices. The fabrication of devices of excellent quality based on MoS2 films is an important research direction. In this study, based on the atomic layer deposition technique, large-area MoS2 films were grown, and top-gate MoS2-based field-effect transistor arrays were fabricated on four substrates (AlN, GaN, sapphire, and SiO2). It was found that the interface defects that were introduced by lattice mismatch and roughness of the growth substrate could cause an exponential (102) drop in mobility. Because of the small lattice mismatch and excellent surface quality, transistors on the AlN substrate have shown an enhanced mobility (10.45 cm2 V-1 s-1) compared to transistors on the other substrates. This study proves that the AlN substrate is a superior substrate for large-area and high-performance MoS2 film synthesis. This result can also be applied in higher-level microelectronic systems, such as in digital logic circuit design.