Latch Design Research Articles

Six-bit 2.7-GS/s 5.4-mW Nyquist complementary metal-oxide semiconductor digital-to-analogue converter for ultra-wideband transceivers

This study presents a 6-bit 2.7 GS/s low-power digital-to-analogue converter (DAC) for ultra-wideband transceivers. A ‘2(thermometer)+4(binary)’ segmented architecture is chosen to reach a compromise between the current source cell's area and the operating speed of the thermometer decoder. In addition, the proposed pseudo-thermometer structure improves the DAC's dynamic performance. The bipolar current source cell and latch clock delay technique are employed to reduce the power consumption in the analogue and digital parts, respectively. Moreover, the compact de-glitch latch presented in this study simplifies the conventional latch design and layout. This DAC was implemented in a standard 0.13 µm 1P8M complementary metal-oxide semiconductor technology with the active area of 0.0585 mm2. The measured differential non-linearity and integral non-linearity are less than 0.09 and 0.11 least significant bit, respectively. The measured spurious-free dynamic range is more than 36 dB over the Nyquist frequency at the sampling frequency of 2.7 GHz. The DAC consumes 5.4 mW with a near-Nyquist sinusoidal output at 2.7 GS/s, resulting in a better figure of merit of 31 fJ/conversion-step than other published arts.

32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches

Single event upset (SEU) experimental heavy ion data and modeling results for CMOS, silicon-on-insulator (SOI), 32 nm and 45 nm stacked and DICE latches are presented. Novel data analysis is shown to be important for hardness assurance where Monte Carlo modeling with a realistic heavy ion track structure, along with a new visualization aid (the Angular Dependent Cross-section Distribution, ADCD), allows one to quickly assess the improvements, or limitations, of a particular latch design. It was found to be an effective technique for making SEU predictions for alternative 32 nm SOI latch layouts.

Passive all-optical polarization switch, binary logic gates, and digital processor

We introduce the passive all-optical polarization switch, which modulates light with light. That switch is used to construct all the binary logic gates of two or more inputs. We discuss the design concepts and the operation of the AND, OR, NAND, and NOR gates as examples. The rest of the 16 logic gates are similarly designed. Cascading of such gates is straightforward as we show and discuss. Cascading in itself does not require a power source, but feedback at this stage of development does. The design and operation of an SR Latch is presented as one of the popular basic sequential devices used for memory cells. That completes the essential components of an all-optical polarization digital processor. The speed of such devices is well above 10 GHz for bulk implementations and is much higher for chip-size implementations. In addition, the presented devices do have the four essential characteristics previously thought unique to the microelectronic ones.

Novel radiation hardened latch design considering process, voltage and temperature variations for nanoscale CMOS technology

As CMOS technology is scaled down, the supply voltage and gate capacitance are reduced, which results in the reduction of charge storing capacity at each node and increase of the susceptibility to external noise in radiation environments. The traditional error tolerant circuit design methods provide very limited protection against the environment noise for storage cells such as latches and memories. In this paper, a novel hardened latch design is proposed and compared with the previous hardened latch designs using 32 nm technology node. Extensive simulation results using HSPICE are reported to show that the proposed hardened latch design achieves 15× improvement of critical charge (Qcrit) with comparable cost in terms of speed and power compared to the most up to date hardened latch design. Moreover, PVT variations have great impact on the reliability of hardened circuit. The proposed latch circuit is also evaluated with the presence of PVT variations and demonstrates higher robustness than other considered robust latch under severe PVT variation condition.

Floating-gate CMOS ternary latch

The design of a novel floating-gate CMOS ternary latch is presented. The design is based on a CMOS latch with level shifters that are realised using floating-gate techniques. The three stable operating points possessed by this circuit allow the cell to realise a ternary latch. The number of operating points possessed by the latch can be set using an external DC voltage. Measurement results from a fabricated prototype in a 0.5 µm CMOS technology are included to demonstrate the design presented.

Reversible Logic-Based Concurrently Testable Latches for Molecular QCA

Nanotechnologies, including molecular quantum dot cellular automata (QCA), are susceptible to high error rates. In this paper, we present the design of concurrently testable latches (D latch, T latch, JK latch, and SR latch), which are based on reversible conservative logic for molecular QCA. Conservative reversible circuits are a specific type of reversible circuits, in which there would be an equal number of 1's in the outputs as there would be on the inputs, in addition to one-to-one mapping. Thus, conservative logic is parity-preserving, i.e., the parity of the input vectors is equal to that of the output vectors. We analyzed the fault patterns in the conservative reversible Fredkin gate due to a single missing/additional cell defect in molecular QCA. We found that if there is a fault in the molecular QCA implementation of Fredkin gate, there is a parity mismatch between the inputs and the outputs, otherwise the inputs parity is the same as outputs parity. Any permanent or transient fault in molecular QCA can be concurrently detected if implemented with the conservative Fredkin gate. The design of QCA layouts and the verification of the latch designs using the QCADesigner and the HDLQ tool are presented.

VCM 액추에이터의 전자기력을 이용한 HDD 래치 설계

Various types of latch designs for hard disk drives using load/unload mechanism have been introduced to protect undesired release motions of a voice coil motor(VCM) actuator from sudden disturbances. Recently, various inertia-type latches have been widely used because locking performance is better than that of other types of latch. However there has been a limit in the inertia type in order to guarantee perfect latch and unlatch operations because of changes in latch/unlatch conditions due to mechanical tolerance and temperature-dependent friction. In this paper, a reliable and robust magnetic latch mechanism is proposed through only simple modifications of coil and yoke shapes in order to overcome the mechanical limit of current inertia-type latches. This new magnetic latch does not have only a simple structure but it also ensures reliable operations and anti-shock performance. The operating mechanism of the proposed latch is theoretically analyzed and optimally designed using an electromagnetic simulation.

A Novel Zero-Insertion-Force (ZIF) Micro $(\mu)$-Connector: Design, Fabrication, and Measurements

This paper presents the design, fabrication, and measured properties of a novel zero-insertion-force (ZIF) micro (mu)-connector. The proposed ZIF mu-connector is shown to remedy a number of problems in the existing microelectromechanical-system-based connectors, such as the wearing effect, the poor signal integrity for high-speed signal transmission, and the lack of latch design. The three-mask and silicon-on-insulator wafers are designed for the simultaneous fabrication of terminals and latches. Prototype connectors are demonstrated with five 1800-mum-long, 100-mum-wide, and 2-mum -high terminals on a 150-mum pitch. The terminals and latches are actuated by electrostatic force to avoid the wearing and kinking during the mating process. The terminal is a multimorph cantilever to form a hooklike out-of-plane shape. The controlled shape of the terminal provides a reliable contact at the interface. The properties of the proposed ZIF mu-connector are measured and analyzed, including the out-of-plane shape of the terminal, driving voltage, dc contact resistance, and the RF characteristics. The potential applications of the ZIF mu-connector include the fine-pitch high-speed interconnection, 3-D reworkable packaging, and the performance enhancement of many existing mu-connectors.

Inertia magnetic latch design considering actuator load unload

Key design considerations of a hard disk drive (HDD) actuator latch with combined magnetic bias and inertia effects are discussed in this paper. At low shock level, the actuator magnetic bias holds it on a parking ramp. At high shock level, the inertia latch locks the actuator from moving out of its parking location. When the two effects are designed to have an overlap at the medium shock level, the combined latch can offer reliable protection at all shock levels. The superior shock protection of the combined latch, however, does not come free. Other than the fundamental mechanical design challenges, extra cares are also needed to load heads from the ramp to media or unload them back to the ramp. Careful magnetic field analysis, shock simulation and component tests are conducted at design phase to ensure complete shock protection. Energy method and dynamics model used for latch design are first introduced in the paper. Mechanical, servo and electronic systems are considered together to create closed loop simulation models, which are used to study firmware controlled load and unload (L/UL) processes, as well as the emergency power off (EPO) unload. The effects of voice coil motor (VCM) torque factor Kt roll-off, actuator magnetic bias and VCM back EMF sensing circuit on L/UL velocity variation and EPO unload performance are examined to ensure system performance.

DVM-03 A Reliable Magnetic Latch Design Using Electro-magnetic Force of VCM Actuator(Drive Mechanisms I,Technical Program of Oral Presentations)

DVM-03 A Reliable Magnetic Latch Design Using Electro-magnetic Force of VCM Actuator(Drive Mechanisms I,Technical Program of Oral Presentations)

Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies

Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.

Self-Voting Dual-Modular-Redundancy Circuits for Single-Event-Transient Mitigation

Dual-modular-redundancy (DMR) architectures use duplication and self-voting asynchronous circuits to mitigate single event transients (SETs). The area and performance of DMR circuitry is evaluated against conventional triple-modular-redundancy (TMR) logic. Benchmark ASIC circuits designed with DMR logic show a 10-24% area improvement for flip-flop designs, and a 33% improvement for latch designs.

Latch Design Techniques for Mitigating Single Event Upsets in 65 nm SOI Device Technology

This paper describes techniques for mitigating single event upsets in master-slave flip-flop latches in 65 nm SOI device technology. Techniques are explained, modeled, and measured with hardware experiments.

Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper presents new techniques to evaluate the energy and delay of flip-flop and latch designs and shows that no single existing design performs well across the wide range of operating regimes present in complex systems. We propose the use of a selection of flip-flop and latch designs, each tuned for different activation patterns and speed requirements. We illustrate our technique on a pipelined MIPS processor datapath running SPECint95 benchmarks, where we reduce total flip-flop and latch energy by over 60% without increasing cycle time. </para>

Single-Event Tolerant Latch Using Cascode-Voltage Switch Logic Gates

A new latch design using Cascode-Voltage Switch Logic gates is evaluated for single event (SE) environments. The latch design is based on the DICE latch design, but with CVSL gates. Calibrated 3D device models for an IBM 130 nm technology were used for mixed-mode simulations of the latch for SE evaluations. Simulation results show that the latch is immune to charge deposition on multiple nodes. The proposed design does require a 60% increase in area and double the power, but is faster than conventional DICE-based latch design

The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 $\mu$m

Four different latch designs are evaluated using heavy ion exposure and simulations. The latches were designed using the Transition AND Gate (TAG) in TSMC 0.35 mum technology. TAG based designs were less vulnerable at lower LETs as compared to unhardened designs. However, 1- and 3-TAG design vulnerability increased at a higher rate with increasing LET than the unhardened design. 4-TAG design did not show any upsets until 170 MeV/mg/cm 2. Simulation results are used to explain the behavior of each of the designs

Design of CMOS Ternary Latches

This paper describes the design methodology of latches with three stable operating points. Open-loop analysis is used to obtain insight into how a conventional binary latch structure can be modified to yield a ternary latch. Four novel ternary latch structures, compatible with a standard CMOS process, are presented. Properties of each latch, including robustness of the ternary behavior, speed, and power dissipation, are described. Measurement results of four RS ternary flip-flops based on the proposed latch structures, fabricated in a standard 0.18-mum CMOS process, are presented. Maximum operating frequency and skew tolerance are reported for each of the four latches

Pawl latch mechanism design and control for load/unload technology

This paper summarizes functions and features of a new latch design, named as pawl latch from herein, for implementation on ramp loading disk drives, where a disk drive with a ramp would allow actuator to stay on the ramp outside the disk when not in use. The new latch system consists of two latch mechanisms: one is inertia latch and the other is magnetic latch. These two latches work together to obtain very reliable non-contact break free latch while maintaining high resistance during rotary shock condition. Simple control method is also presented to alleviate audible noise issue generated using the pawl latch mechanism.

Design analysis and circuit enhancements for high-speed bipolar flip-flops

The design of high-speed current mode logic latches is discussed, using analytical expressions for delay. An open circuit time constant method is utilized throughout this paper, though similar results were obtained from a charge control analysis. Emphasis is placed on the variables that are under the control of the circuit designer, as opposed to the device designer. Circuit delay is calculated with respect to device area, current density, amplitude, and a keep-alive current. In particular, the keep-alive current gives the circuit designer control over the average transconductance of switching transistors, independent of their bias currents. The cost of the keep-alive current is the loss of output amplitude. The effects of transmission lines and peaking inductors are discussed in a qualitative manner. Latch designs were tested with static divide-by-two frequency dividers. Results of several dividers (both SiGe and InP) are shown and compared with the theory.

Edge triggered pulse latch design with delayed latching edge for radiation hardened application

We describe a novel edge triggered pulse latch design with delayed latching edge. Combined with dual interlocked cell (DICE) slave latch stage, the presented design is radiation hardened to both static single event upset (SEU) and dynamic single event transient (SET) on its internal sensitive nodes. Delayed latching edge design enables a new block level radiation hardening circuit design approach to trade timing resources in nontiming critical paths with the radiation hardness.