The Effectiveness of TAG or Guard-Gates in SET Suppression Using Delay and Dual-Rail Configurations at 0.35 $\mu$m

Abstract

Four different latch designs are evaluated using heavy ion exposure and simulations. The latches were designed using the Transition AND Gate (TAG) in TSMC 0.35 mum technology. TAG based designs were less vulnerable at lower LETs as compared to unhardened designs. However, 1- and 3-TAG design vulnerability increased at a higher rate with increasing LET than the unhardened design. 4-TAG design did not show any upsets until 170 MeV/mg/cm 2. Simulation results are used to explain the behavior of each of the designs