Interconnect Design Research Articles

CHARACTERISATION OF BONE-REGENERATING SCAFFOLDS PRODUCED THROUGH LITHOGRAPHY-BASED CERAMIC MANUFACTURING

Lithography-based ceramic manufacturing (LCM) is an additive manufacturing (AM) technology that builds custom-designed, three-dimensional ceramic parts layer by layer. The level of precision of the process allows for the printing of custom-made interconnected lattices and designs suitable for bone implants. This study investigated the LCM printability of various lattice structures with the hydroxyapatite (HA480) supplied by Lithoz. Different lattice structures were characterised. The microscopic structure, the composition, and the surface roughness of the test specimens were determined. To obtain the mechanical properties of the structures, compression tests were performed. The observed micropores of ±3 µm and the macropores of ±320 µm were suitable for bone cell growth. The measured microhardness of HA480 was 556±25 HV in the built direction and 559±27 HV perpendicular to the built direction. The compressive strength of the rhombic dodecahedron lattice structure was 4±0.5 MPa, and was superior to other tested lattices. From the results it was concluded that lattice structures produced through LCM have the potential to be used to produce customised bone-regenerating scaffolds.

Research on UI visual interface design of local museum under digital background

With the rapid development of mobile internet, competition among similar software has become increasingly fierce. To stand out in this highly competitive market, in addition to having unique features, emphasis must be placed on creative UI design and finely categorizing it into mobile interactive interface design apps. This article's "Cloud Tourism" museum app relies on Internet of Things technology, mobile communication technology, cloud computing technology, artificial intelligence technology, and mobile interaction technology to provide users with high-quality experiences through perceptual, interconnected, intelligent, and flat design. This article provides a detailed introduction to the main design process, with the aim of making the interaction between people and software more comfortable, simple, and natural.

Design Theory for Societal Digital Transformation: The Case of Digital Global Health

With societal challenges, including but not limited to human development, equity, social justice, and climate change, societal-level digital transformation (SDT) is of imminent relevance and theoretical interest. While building on local-level efforts, societal-level transformation is a nonlinear extension of the local level. Unfortunately, academic discourse on digital transformation has largely left SDT unaccounted for. Drawing on more than 25 years of intensive, interventionist research engagement with the digital transformation of public healthcare information management and delivery in more than 80 countries in the Global South, we contribute to theorizing SDT in the form of a design theory consisting of six interconnected design principles. These design principles articulate the interplay and tensions of accommodating over time increased diversity and flexibility in digital solutions, while simultaneously connecting local, national, and regional/ global efforts.

Effects of underfill on wideband flip-chip packaging for 5G millimeter-wave applications

This letter investigates the effects of the underfill on the wideband flip-chip packaging for 5G millimeter-wave (mm-Wave) applications. For accurate interconnect design, a new hybrid equivalent circuit model is proposed. Targeting at the phased array systems with high density I/Os, a compact anti-pad structure is implemented and co-designed with the high impedance transmission line and the low-cost 90 μm solder balls, compensating the flip-chip capacitive parasitics and realizing the compact low-loss interconnect. To evaluate the underfill effect on the interconnect parasitics, both theoretical analyses and simulations are undertaken. For demonstration, by using a glass substrate with the fan-out process, back-to-back flip-chip packaging structures are designed, fabricated, and measured. Measured results demonstrate that with and without underfill U8410-99 the interconnect return loss is better than 20 and 10 dB from DC to 90 GHz, with an insertion loss of 0.2 and 0.45dB at 60GHz, respectively.

Thermal-inert and ohmic-contact interface for high performance half-Heusler based thermoelectric generator

Unsatisfied electrode bonding in half-Heusler devices renders thermal damage and large efficiency loss, which limits their practical service at high temperatures. Here, we develop a thermodynamic strategy to screen barrier layer elements. Theoretically, we found that the interface between VIIB elements and half-Heuslers possesses near-zero interfacial reaction energy and large atomic diffusion barrier. Experimentally, such an interphase proves to be the atomic direct bonding and has high thermal stability at 1073 K, leading to ideal ohmic contact. Such thermally inert and ohmic contact interface enable modules stably to work at elevated temperature up to 1100 K, which releases the peak performance of half-Heuslers and in turn boosts the energy conversion efficiencies to the records of 11.1% and 13.3% for half-Heusler single-stage and half-Heusler/Bi2Te3 segmented modules. This design strategy provides a feasible solution for the high-temperature half-Heusler generators and gives enlightenment for other package interconnection design of electronic devices.

Physics-of-degradation-based life prediction of solder interconnects of long-life solar arrays in low-earth orbit

Exact prediction of lifespans of solder interconnects is critical for designing reliable solar photovoltaic systems that operate for a long time across a wide range of temperatures in low earth orbit, but pertinent prediction methodology has rarely been investigated. Here, a systematic approach for analyzing the fatigue life of the solder interconnects was developed concurrently using experimental, computational, and analytical methods. Physics of failure was examined using thermal cycling, thermal aging, and materials characterization. Solder interconnect geometry as well as strain distribution and evolution were determined through equilibrium liquid surface simulation and finite element simulation. Microstructure evolution modeling, constitutive equation fitting, and fatigue model calibration were conducted to reliably predict solder interconnect lifetime. Using this integrated approach to busbar-to-wire solder interconnects in photovoltaic systems, we have demonstrated that increasing the stand-off height of solder interconnects can delay the onset of the fatigue cracks and prolong the total fatigue life. The interconnects with large solder amount go through long life due to slow crack propagation with low averaged plastic work, but they possess nearly the same number of cycles to fatigue crack initiation because of relatively fixed plastic strain range under thermal cycling. The approach proposed would be useful to inspire the design of robust interconnects in photovoltaic systems that survive harsh thermal cycling (−90 to + 130 °C).

Optimal interconnection of three‐terminal tandem solar cells

AbstractThree‐terminal (3T) tandem solar cells require an adapted module integration scheme in order to explore their full efficiency potential. The three terminals allow to extract the power of the top and bottom cell separately. In a cell string, the wide bandgap top cells are interconnected in parallel to multiple bottom cells resulting in a parallel/series interconnection. This interconnection scheme affects the operation of the subcells, the resulting current path between the subcells, the layout of the cell interconnects, and the system level. Here, we analyze by simulations and experiments the aspects of the module integration of series‐ and reverse‐connected 3T cells with their practical impact on module processes and performance as well as the effect of varying voltage ratios on the string‐end losses. If the subcells are connected in series, the module integration requires insulation layers and significantly longer interconnects compared to devices with reverse‐connected subcells. Tandem devices with a reverse connection and a voltage ratio between top and bottom cell of 2:1 allow a lean interconnection design and low integration losses. We present an approach for the integration of bypass diodes for the protection against shading effects that allow to minimize string‐end and shading losses for a system of modules featuring 3T cells.

Design Space Exploration of Interconnect Materials for Cryogenic Operation: Electrical and Thermal Analyses

With Copper (Cu) Interconnects causing performance bottleneck at single nanometer nodes due to increase in resistivity size effects viz., grain boundary scattering and surface scattering, there has always been scavenging for alternate interconnect materials. Although the Cu resistivity value decreases at cryogenic temperature, the problems continue to persist. In this work, we study three alternate interconnect materials specifically for 77K High Performance Compute applications. We select the materials based on their resistivity value at 77K for 7nm node computed using Fuchs-Sondheimer-Mayadas-Shatzkes (FS-MS) models. We analyze the delay of the interconnects, understand repeater insertion as a function of wire length, evaluate repeater count and energy at system level and perform IR drop analysis by showing through detailed analytical models that Ru, Rh and Al can provide appreciable improvements over Cu at 77K. The delay of interconnects reduces by 1-3.75% for Ru, 1.5-7.25% for Rh and 4.4-17.8% for Al across the BEOL stack while repeater counts decrease by 10%, 15% and 37% for Ru, Rh and Al respectively at 77K. We investigate thermal and reliability aspects of interconnect design including electromigration, Joule Heating and maximum allowed current densities again proving that Ru (9%), Rh (18%) and Al (63%) outperform Cu at 77K. Finally, we study the effects of various Low-k dielectric materials on the interconnect capacitance and thermal behavior for Cu as well as three alternate materials noting that, even though thermal conductivity of dielectrics decrease at 77K, the Joule Heating will not be as worse as one might expect.

Creep-fatigue lifetime estimation of efficient photovoltaic module ribbon interconnections

As the solar PV harvesting energy system are becoming more important sector of renewable energy day to day, improving the efficiency of the solar PV module and reducing the cost of modules are receiving more attentions of PV module manufacturers. Design of the PV module interconnection ribbons is one of the main focus for developing the efficiency of the PV modules and improving the reliability of the modules. In the last decade, new designs for the PV module interconnection ribbon have been introduced, however, there is still a need to optimize their configuration and geometry to achieve higher reliability without dropping the efficiency of the PV modules. Indeed, solely using the wider interconnection ribbons (to provide more joint length) may increase the reliability of the module, but it directly reduces the efficiency of module due to more shading effect. This study provides the results for determining the optimal design for long-term reliability of PV module interconnections. Three main PV module ribbon interconnection designs including Conventional Ribbon (CR), Light-Capturing Ribbon (LCR), and Multi-Busbar (MBB) interconnections are compared in terms of number of cycles to creep-fatigue failure. This study uses the FEM simulation and creep-fatigue reliability formulations to find the effect of the main geometrical parameters on the failure of different PV module ribbon interconnection designs. The finding showed that the MBB interconnections has up to 15 % higher creep-fatigue lifetime compared to the LCR and the CR interconnections.

(Digital Presentation) Electrodeposition of Re on Aerosol Jet Printed Metal Seed Layers on Flexible Substrates

Quantum computers (QCs) are expected to run advanced algorithms to solve currently intractable challenges in chemistry simulations, cryptography, medicine, and finance.[1] The Josephson Junction based qubits that power a quantum computer must reside in a cryogenically cooled chamber at 10 mK. Communications with this chip is currently carried out with a chandelier of rigid cables.[2] A flexible cable containing superconducting interconnect lines could in principle simplify the design of QC interconnects and lead to improvement in qubit density and efficiency. We have previously demonstrated the use of aerosol jet printing (AJP) for the patterning of electrodeposited Cu and Ni [3]. We have also recently reported on the development of a water-in-salt method to electrodeposit superconducting Re on evaporated Au on Si substrates. These Re components have a critical temperature above 4.2 K, which makes the superconductivity easily accessible with liquid He cooling[4].We report for the first time the metallization of flexible Kapton substrates with printed Au and Ag nanoparticle inks by aerosol jet printing as the seed for superconductor electrodeposition. Electrodeposition of Re onto the printed structures was performed using the water-in-salt method. ASTM D3359 tests demonstrated that Au has superior adhesion to Kapton, while the Ag seed does not survive rhenium deposition, potentially due to the high internal stress of Re. Further, improved adhesion was demonstrated when Kapton substrates were roughened with 1200 grit sandpaper. Electrodeposited Re on AJP Au seed layer on flexible Kapton substrates, as shown in Figure 1, demonstrated a superconducting transition temperature of 6K. In addition, electrodeposited Re on Au survived 200 cycles of flexure testing under >30 MPa load and 1.2% strain. These efforts demonstrate the proof-of-principle for patterning of superconducting interconnects for the further development of QCs. SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525. SAND2022-11522 A References [1] F. Bova, A. Goldfarb, and R.G. Melko “Commercial Applications of Quantum Computing.” EPJ Quantum Tech. (2021) 8:2.[2] S. Krinner, S. Storz, P. Kurpiers, P. Magnard, J. Heinsoo, R. Keller, J. Lütolf, C. Eichler & A. Wallraff. “Engineering cryogenic setups for 100-qubit scale superconducting circuit systems.” EPJ Quantum Tech. (2019) 6:2.[3] L. K. Tsui, S. C. Kayser, S. A. Strong, and J. M. Lavin, “High Resolution Aerosol Jet Printed Components with Electrodeposition-Enhanced Conductance.” ECS J. Solid State Sci. Tech. (2021). 10, 047001.[4] W. D. Sides, E. Hassani, D. P. Pappas, Y. Hu, T. S. Oh, Q. Huang “Grain growth and superconductivity of rhenium electrodeposited from water-in-salt electrolytes.” J. App. Phys. (2020). 127, 085301.Figure 1. (a) Photograph of a well adhered Re on Au sample. (b) Superconducting transition data for Re on printed Au on Kapton. Figure 1

(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems

Fan-out wafer-level packaging has become during the last decade an iconic part of the More Than Moore trend. Emerging in the mid-2000s and early declined in embedded wafer level ball grid array (eWLB), it has since gained popularity for the realization of high-potential systems-in-package (SiP).The basic technology is based on the reconstruction of wafers from individual chips. After embedding chips with an epoxy mold compound (EMC), electrical connections are processed in the form of redistribution layers (RDL) to fan-out signals from chip I/Os to solder balls, whose dimensions are compatible with direct soldering to a printed circuit board. Eliminating the need for intermediate laminated substrates, it has enabled the integration of systems with high performance at reduced cost and footprint. It has also paved the way for applications that would have been difficult to address with conventional packaging.In a resolutely heterogeneous declination of this technology, the co-integration of several chips in a single and dense package has allowed processing multi-chip SiPs including CMOS circuits, memories, radio-frequency (RF) chips and passive components with reduced interconnect length. It is indeed possible to combine in the same package different materials such as Si, SiC, GaN, AsGa. This property gives FOWLP technology unique advantages in terms of cost and versatility that make it attractive in many application areas.Two trends seem to take advantage of this technology. On one hand, the realization of high performance SiPs integrating miniaturized CMOS processors and dense, high bandwidth memories with aggressive interconnects design rules. On the other hand, highly heterogeneous systems mixing semiconductors, especially in the field of wireless telecommunications. For over a decade, RF devices have been taking advantage of FOWLP to build advanced packages with shorter interconnects. Mass production has been reached since 2009 for automotive radars, baseband processors, RF transceivers and power management circuits. More recently, the millimeter wave market has gained interest with the development of 5G at high frequencies (>6 GHz), where the fan-out area becomes an opportunity to embed high quality passives and antennas.CEA-Leti has been studying this technology from its inception, with pioneering work since 2005 outlining wafer reconstruction for heterogeneous integration. At the heart of integration, the epoxy mold compound (EMC) is the way to reconstruct the wafer. By becoming the mechanical link between the different chips, it plays a crucial role during the entire process. On another level, the interconnects constitute the final purpose of the FOWLP integration: RDL layers create the link between chips in heterogeneous SiPs, as well as the link between the SiP and the outside world. These two components must be mastered to ensure functionality and performance of final SiPs.Among various available configurations, the die first scheme consists in positioning chips before molding and processing the interconnects. In RDL 1st scheme the interconnections are, conversely, made before chips are placed. Although these approaches sometimes compete, they generally meet different specifications. Nevertheless, all the configurations share integration issues related to the materials and processes involved. Some of the classic issues met in FOWLP include wafer deformation due to CTE mismatches, die shift during the process and the difficult task of heat dissipation in dense SiPs with increased power densities. We will show how useful the characterization techniques are to develop and improve the overall process, in order to reach the targeted specifications.To illustrate these elements, a detailed description of the technology built up for the realization of heterogeneous systems will be given, such as 5G base stations transceiver operating at 28 GHz including GaN and AsGa chips. We will also present original options implemented to meet the needs of other application fields, and develop our strategy regarding thermal dissipation for future SiPs.In a FOWLP approach, three-dimensional integration is also possible thanks to a technological toolbox that includes, in addition to RDL and solder balls, vertical connections such as Through-Mold Via (TMV). We will describe an original approach developed at CEA-Leti for the fabrication of high aspect ratio TMVs, with a demonstration of 225 µm high and 100 µm pitch TMV for the realization of 3D SiP with high interconnection density. Figure 1

3D printed freestanding ZnSe/NC anodes for Li-ion microbatteries

The rapid development of micro/nanomanufactured integrated microsystems in recent years requires high performance micro energy storage devices (MESDs). Li-ion microbatteries (LIMBs) are the most studied MESDs, but the low mass loading of active materials and the less-than-perfect energy density hinder their further application. A 3D printed ZnSe/N-doped carbon (ZnSe/NC) electrode was designed and fabricated by extrusion-based 3D printing and a post-treatment strategy as the anode of LIMBs. The high-capacity ZnSe nanoparticles are confined in the NC, where the NC not only improves the conductivity but also acts as a buffer layer to reduce the volume expansion and provide additional active sites for electrochemical reactions. The interconnected design of the 3D printed electrode is good for fast mass transfer and ion transport. A freestanding 3D printed ZnSe/NC electrode with a high mass loading of 3.15 mg cm−2 was achieved by direct ink printing, which had a superior energy density and decent reversibility in high-power LIMBs. This strategy can be used for other high-performance electrodes to achieve a high-mass-loading of active materials for microbatteries, opening up a new way to construct advanced MESDs.

Power optimization using current-mode signalling technique for IoT applications

There have been significant advances in the scope of smart devices. These smart technologies allow billions of devices to communicate with each other over the internet, thus coining the term Internet of things (IoT). IoT is a system that combines sensing, computing, storage, and communication to sense the physical environment and respond accordingly. All the devices connected in IoT applications are connected through an interconnection. These interconnections allow the objects to communicate with each other and produce an output. But with an increasing demand for small devices, comes the concerns with the interconnect performance such as power dissipation and delay. In this paper, an interconnect design is simulated with a current mode signalling technique to reduce power consumption and delay in the interconnect circuit.

A combined Control by Interconnection—Model Predictive Control design for constrained Port-Hamiltonian systems

This paper proposes a Control by Interconnection design, for a class of constrained Port-Hamiltonian systems, which is based on an associated Model Predictive Control optimization problem. This associated optimization problem allows to consider both state and input constraints simultaneously. Based on the first order Karush–Kuhn–Tucker optimality condition, the primal–dual gradient method is then used to build a passive feedback controller, derived from the MPC-induced optimization problem. The resulting passive controller is coupled with the original Port-Hamiltonian system through a power-preserving interconnection, in order to guarantee both the closed-loop stability and constraints satisfaction, but not the optimality anymore. Comments on parameters tuning for the proposed control design, together with validations of the approach through simulations first on a linear LC circuit, then on a nonlinear Permanent Magnet Synchronous Motor and comparisons with a classical MPC design, are provided to discuss the effectiveness of the approach. • A controller combining CbI and MPC is proposed to tackle PHs with constraints. • The MPC principle is used to deal with both state and input constraints. • The CbI takes advantage of the PHs passivity for convergence and stability analysis. • The primal–dual gradient method significantly reduces the computational effort. • The explicit form of the controller facilitates implementation and maintenance.

Classification of inter-modular connections for stiffness and strength in sway corner-supported steel modular frames

Corner-supported modular steel buildings, made of volumetric bespoke prefabricated units, are one of the most efficient construction systems for the next generation of prefabricated prefinished building construction. In these systems, the influence of connections between the units, so-called inter-connections, on the distribution of forces, moments, stability, and deformations of the frame is the key to the overall structural performance that differentiates the design of these systems from that of their conventional counterparts. In the design of modular buildings, the structural properties of inter-connections, such as stiffness, strength, and rotation capacity, are elements directly impacting their performance. This paper proposes a classification system for rotational stiffness and strength properties of inter-connections in sway corner-supported modular frames. The stiffness' boundary values corresponding to the rigid/semi-rigid and semi-rigid/nominally-pinned zones are represented by parametric charts based on the variation of relative bending stiffness ratios of elements such as beams, columns, and joints. To develop the classification system corresponding to stiffness properties of inter-connections, three performance criteria are assumed as (i) buckling criterion, which represents the classification based on the ultimate limit state; (ii) displacement/drift criterion, which considers the behaviour of the structure in the serviceability limit state; and (iii) combined buckling and displacement/drift criterion at the ultimate limit state. Furthermore, inter-connections are classified into three categories of fully-strength, partial-strength, and nominally-pinned in terms of their strength properties based on the ultimate moment capacity of inter-connections. The proposed classification system can be employed in the initial phase of a modular structure design to classify joints, and select a proper design method and process according to their category. Numerical examples are included to verify the validity of the proposed classification system. Finally, design recommendations are suggested for the accurate design of inter-connections in sway corner-supported modular frames without the need for complicated nonlinear analyses.

Desain Interkoneksi Jaringan Menggunakan Vpn Internet Untuk Mendukung Sistem Pemerintahan Berbasis Elektronik

The rapid advance in information and communication technologies developement has greatly facilitated the development of electronic government worldwide. This can be seen from the various applications of information technology in government agencies, including integrated Electronic-Based Government System (SPBE). Numerous government agencies have implemented SPBE services for their daily operations. However, there are not infrequently the initiative for the existence of ICT infrastructure in several government institutions has some issues because due to various aims and backgrounds in developing it. The issues such, development of ICT network infrastructure is less efficient and effectiveness, the absence of a standard network system configuration, and the network security system underestimated. Therefore, this research will be designed and built ogan komering ulu regency government network systems using IPv4-based internet VPN with Network Development Life Cycle (NDLC) method. The purpose of this research is to provide a model of uniformity in the preparation of government network configurations, realize network interconnection between government agencies that make better utilization of network infrastructure, and support SPBE in Goverment of Ogan Komering Ulu District and improve aspects of network security in government. The results of this study indicate that by using a VPN network interconnection design, private network communication that passes through the public network (internet) will be more secure so that data confidentiality is maintained. The quality of data exchange in the form of images, sound, and text is better with a stable speed and maintained security. The use of IPv4 for network interconnection is used to reach all government agencies in the Scope of Government of Ogan Komering Ulu Regency.

High-Speed Interconnects: History, Evolution, and the Road Ahead

An integrated circuit (IC), or chip, is a set of electronic circuits and components placed on a tiny planar silicon (Si) semiconductor substrate. These electronics circuits and components are electrically connected to one another with the help of planar and vertical conductor elements known as <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">interconnects</i> . This article presents a detailed overview of the evolution of interconnects, highlighting the technological milestones that have been achieved during the past four decades. Interconnects form the backbone of signal communication among devices on a chip and between chips on a printed circuit board (PCB). The layout and design of interconnects on an IC are vital to the chip’s performance, functionality, reliability, efficiency, and overall fabrication yield.

Power-delay-product optimal repeater design for horizontal and vertical multilayer graphene nanoribbon interconnects

Power-delay-product optimal repeater design for horizontal and vertical multilayer graphene nanoribbon interconnects

Polymer waveguide photonic interconnect for multichip communications-based heterogeneous integration

An on-package optical interconnect design is proposed for the first time, with silicon photonics in conjunction with the polymer-on-glass interposer technology to enable heterogeneous integration. Glass substrates are used for low-cost, high reliability packaging while silicon photonics allows for high-speed modulation and wavelength division multiplexing within a small footprint. By combining silicon-photonic and benzo-cyclobutene-on-glass interposer technologies, we propose a scalable on-package photonic interconnect that can provide data rates >224 Gb / s for medium-reach links. Our proposed interconnect considers microring modulators and high-speed detectors available in photonic-foundry processes. We present the power-budget analysis to identify the key limiting parameters toward achieving an energy consumption of < 1 pJ / bit.

Understanding hot interconnects with an extensive benchmark survey

Understanding the designs and performance characterizations of hot interconnects on modern data center and high-performance computing (HPC) clusters is a fruitful research topic in recent years. The rapid and continuous growth of high-bandwidth and low-latency communication requirements for various types of data center and HPC applications (such as big data, deep learning, and microservices) has been pushing the envelope of advanced interconnect designs. We believe this is high time to investigate the performance characterizations of representative hot interconnects with different benchmarks. Hence, this paper presents an extensive survey of state-of-the-art hot interconnects on data center and HPC clusters and the associated representative benchmarks to help the community to better understand modern interconnects. In addition, we characterize these interconnects by the related benchmarks under different application scenarios. We provide our perspectives on benchmarking data center interconnects based on our survey, experiments, and results.