(Invited) Fan-out Wafer-Level Packaging: Opportunities and Challenges Towards Heterogeneous Systems

Abstract

Fan-out wafer-level packaging has become during the last decade an iconic part of the More Than Moore trend. Emerging in the mid-2000s and early declined in embedded wafer level ball grid array (eWLB), it has since gained popularity for the realization of high-potential systems-in-package (SiP).The basic technology is based on the reconstruction of wafers from individual chips. After embedding chips with an epoxy mold compound (EMC), electrical connections are processed in the form of redistribution layers (RDL) to fan-out signals from chip I/Os to solder balls, whose dimensions are compatible with direct soldering to a printed circuit board. Eliminating the need for intermediate laminated substrates, it has enabled the integration of systems with high performance at reduced cost and footprint. It has also paved the way for applications that would have been difficult to address with conventional packaging.In a resolutely heterogeneous declination of this technology, the co-integration of several chips in a single and dense package has allowed processing multi-chip SiPs including CMOS circuits, memories, radio-frequency (RF) chips and passive components with reduced interconnect length. It is indeed possible to combine in the same package different materials such as Si, SiC, GaN, AsGa. This property gives FOWLP technology unique advantages in terms of cost and versatility that make it attractive in many application areas.Two trends seem to take advantage of this technology. On one hand, the realization of high performance SiPs integrating miniaturized CMOS processors and dense, high bandwidth memories with aggressive interconnects design rules. On the other hand, highly heterogeneous systems mixing semiconductors, especially in the field of wireless telecommunications. For over a decade, RF devices have been taking advantage of FOWLP to build advanced packages with shorter interconnects. Mass production has been reached since 2009 for automotive radars, baseband processors, RF transceivers and power management circuits. More recently, the millimeter wave market has gained interest with the development of 5G at high frequencies (>6 GHz), where the fan-out area becomes an opportunity to embed high quality passives and antennas.CEA-Leti has been studying this technology from its inception, with pioneering work since 2005 outlining wafer reconstruction for heterogeneous integration. At the heart of integration, the epoxy mold compound (EMC) is the way to reconstruct the wafer. By becoming the mechanical link between the different chips, it plays a crucial role during the entire process. On another level, the interconnects constitute the final purpose of the FOWLP integration: RDL layers create the link between chips in heterogeneous SiPs, as well as the link between the SiP and the outside world. These two components must be mastered to ensure functionality and performance of final SiPs.Among various available configurations, the die first scheme consists in positioning chips before molding and processing the interconnects. In RDL 1st scheme the interconnections are, conversely, made before chips are placed. Although these approaches sometimes compete, they generally meet different specifications. Nevertheless, all the configurations share integration issues related to the materials and processes involved. Some of the classic issues met in FOWLP include wafer deformation due to CTE mismatches, die shift during the process and the difficult task of heat dissipation in dense SiPs with increased power densities. We will show how useful the characterization techniques are to develop and improve the overall process, in order to reach the targeted specifications.To illustrate these elements, a detailed description of the technology built up for the realization of heterogeneous systems will be given, such as 5G base stations transceiver operating at 28 GHz including GaN and AsGa chips. We will also present original options implemented to meet the needs of other application fields, and develop our strategy regarding thermal dissipation for future SiPs.In a FOWLP approach, three-dimensional integration is also possible thanks to a technological toolbox that includes, in addition to RDL and solder balls, vertical connections such as Through-Mold Via (TMV). We will describe an original approach developed at CEA-Leti for the fabrication of high aspect ratio TMVs, with a demonstration of 225 µm high and 100 µm pitch TMV for the realization of 3D SiP with high interconnection density. Figure 1