IC Design Research Articles

A Review of Miniaturized Advanced IC Rectenna for Energy Harvesting Applications

This article presents a review of different types of miniaturized rectenna integrated circuits IC used for energy harvesting applications such as medical applications. The rectenna design consists of two basic components: an embedded antenna that collects radio-frequency RF energy from the surrounding environment, and the rectifier circuit that converts AC-RF energy values into DC voltage for usage in low-power electronics devices such as implantable medical devices (IMDs). Microwave Schottky diodes HSMS-285x and SMS-763x series are used as a voltage doubler rectifier with an implanted antenna to improve conversion efficiency and the output voltage at a given input power and appropriate load. There are many challenges in the implantable rectenna IC design such as biocompatibility, miniaturization, patient safety, compact size, resonant frequency, bandwidth, radiation efficiency, and insensitivity to detuning. This review article summarizes the overall rectenna research carried out for new different design strategies in implant medical applications that operated at industrial scientific, and medical (ISM) bands such as 2.45GHz and 5.8GHz.

Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process

Complementary field-effect transistor (CFET) is a future transistor type with a high potential to be used beyond 3-nm technology nodes. Despite its high future value, studies related to CFETs mostly focused on the device aspects. In other words, the path of CFET full-chip IC design is not fully demystified, knowing that various design factors/steps (such as schematic, layout, parasitics, design flow) must be considered on top of device traits for full-chip level IC. Therefore, this study focuses on enlightening the remaining factors/steps for full-chip IC design. In detail, we notify the importance of parasitics from various aspects of CFET design and provide optimization solutions. Compared to nanosheet FET (NSFET) on the full-chip scale, CFET shows a reduction of the area by −48.2%, power by −29.4%, total wirelength by −32.5%, and the number of cells by −18.1%.

Temperature and Power Supply Compensated CMOS Clock Circuit Based on Ring Oscillator

Improved performance operational amplifier demand has continuously increased. IC designers use the charge pump technique as an advanced solution to implement the amplifier’s rail−to−rail input stage, but the need for a large load capacitor is a serious downside. To reduce this passive component value, high−frequency clock circuits with a 50% duty cycle should be implemented. This paper focuses on designing such a circuit that is further compensated with temperature and power supply, maintaining these performances even when process variations occur, starting from a ring oscillator as the architecture core. A pre−layout 50 MHz center frequency at 25 °C with a 1.6 temperature percentage error was achieved. Post−layout simulations to account for parasitic effects were also performed, with a 48.9 MHz center frequency reached. Distinct methods that control the frequency variation were discussed and established. Performance comparison of the designed PLL with previously reported clock circuits in the CMOS process was concluded, with superior results such as power consumption, die area, and temperature range accomplished.

Bus-Aware IO Alignment Considering Length-Matching Constraints in 3-D IC Designs

Bus-Aware IO Alignment Considering Length-Matching Constraints in 3-D IC Designs

Through the Looking Glass—The 2023 Edition: Trends in solid-state circuits from ISSCC

The International Solid-State Circuits Conference (ISSCC) is the flagship conference of the IEEE Solid-State Circuits Society. The theme for ISSCC 2023 is “Building on 70 Years of Innovation in Solid-State Circuit Design.” The IC design community has proved to be agile and resilient in a world scarred by the worldwide pandemic, and this year’s ISSCC commemorates the 70th anniversary of ISSCC with an edition that is more than ever focused on innovation. To enhance our lives and support increasingly more innovative developments, ISSCC promotes and shares new circuit ideas with potential to advance the state of the art for IC design and enable systems with ever-improving functionality and efficiency.

IEEE SSCS Beijing Chapter Organizes Five ISSCC Promotion Seminars [Chapters

The IEEE Solid-State Circuits Society (SSCS) Beijing Chapter, together with the SSCS Tsinghua Student Chapter, organized five International Solid-State Circuits Conference (ISSCC) promotion seminars from late March to April, at Tsinghua University, Peking University, Beijing University of Technology, Institute of Semiconductors, Chinese Academy of Sciences, and Beijing University of Posts and Telecommunications, respectively. The participants were mainly undergraduates majoring in electronic engineering and junior graduate students majoring in IC design.

Разработка доверенных средств проектирования ИС в базисе гетерогенных ПЛИС

This paper focuses on the development of trusted tools for designing digital circuits in the basis of heterogeneous field programmable gate arrays (FPGAs). Designing heterogeneous FPGAs is one of the most actively growing areas in Russian microelectronics at present. The paper discusses the main problems and challenges associated with the development of trusted computer-aided design tools. The authors propose a relevant approach to the development of a computer-aided design system based on the use of open-source software tools together with proprietary developments for its critical components. This approach allows to increase the efficiency and reliability of the design process in the basis of heterogeneous FPGAs. The paper considers such stages of the design flow in the basis of heterogeneous FPGAs as logic synthesis and technology mapping, different stages of layout synthesis and static timing analysis. The work is of interest to specialists in the field of microelectronics, as well as to researchers involved in the development of IC design tools and systems. The research results contribute to the improvement of existing IC design methods and tools, as well as to the development and expansion of the Russian electronic component base.

Teaching IC Design: From Concepts to Testing a Fabricated Custom Chip [Society News

Teaching IC Design: From Concepts to Testing a Fabricated Custom Chip [Society News

Continuous-Time Analog Filters for Audio Edge Intelligence: Review on Circuit Designs [Feature

Edge audio devices can reduce data bandwidth requirements by pre-processing input speech on the device before transmission to the cloud. As edge devices are required to ensure always-on operation, their stringent power constraints pose several design challenges and force IC designers to look for solutions that use low standby power. One promising bio-inspired approach is to combine the continuous-time analog filter channels with a small memory footprint deep neural network that is trained on edge tasks such as keyword spotting, thereby allowing all blocks to be embedded in an IC. This paper reviews the historical background of the continuous-time analog filter circuits that have been used as feature extractors for current edge audio devices. Starting from the interpretation of a basic biquad filter as a two-integrator-loop topology, we introduce the progression in the design of second-order low-pass and band-pass filters ranging from OTA-based to source-follower-based architectures. We also derive and analyze the small-signal transfer function and discuss their usage in edge audio applications.

ISSCC 2023 Evening Event: What Will Be the Essential Skills for IC Designers in the Next Decade? [Conference Reports

Provides society information that may include news, reviews or technical notes that should be of interest to practitioners and researchers.

Evolution of ESD Robust IC Design: How ESD design and ESD control have changed our industry

Evolution of ESD Robust IC Design: How ESD design and ESD control have changed our industry

Параллельная реализация алгоритма исправления нарушений антенных правил в маршруте OpenLane

The open IC design flow OpenLane make available the RTL-to-GDS design flow to be implemented, but still some tasks remain unsolved. An example of such task is the correction of antenna rules violations. The detection tools for this procedure are the part of the OpenLane flow but it does not contain any tools for avoiding them. In this article the software is presented that has been developed and allows to avoid violations of antenna rules based on input data in the form of LEF file with information about the standard cell library and DEF file with information about the placement and routing of the design. A parallel implementation is also described; we show the results of more than 60% gain in time with using parallel version in comparison with sequential version. The article describes both the developed algorithm and the software built on its basis, the capability of embedding into an open OpenLane flow, and an example of embedding script code. The use of the developed software makes it possible to correct a significant part of antenna rules violations, thereby increasing the yield.

A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

In VLSI circuit design, physical design is one of the main steps in placing the circuit into the chip area. Floorplanning is a crucial step in the physical design of IC design, which generates a blueprint for the placement of circuit modules into the chip. A floorplanning step accepts a netlist as its input, given by the circuit-partitioning step of physical design. The floorplanning step generates optimal placements for the circuit modules. The netlist contains the modules’ dimensions, size, and interconnect information. During the floorplan generation, the chip area, wire length required for connecting modules and the heat generated by the chips can be estimated. A good floorplan makes placements and routing simple. In order to improve the circuit performance by minimizing chip area, wire length, and peak temperature, it is essential to generate an optimized floorplan by developing metaheuristic optimization algorithms. A novel Hybridized Multicriteria Ant Colony and Firefly Optimization (HMAC-FO) technique is introduced to generate an optimized floorplan. The primary focus of HMAC-FO technique is to design a model for generating efficient floorplanning. The standard MCNC benchmark dataset has a number of modules with their connections. Firefly optimization is the main algorithm in HMAC-FO, which has been used in generating efficient floorplan with the optimized area, wire length and thermal. The firefly algorithm initially requires some number of solutions as the fireflies’ population. In the firefly algorithm, usually, the populations are generated randomly. But, to improve the firefly optimization algorithm’s performance and obtain better optimum results, the proposed technique uses ACO to generate the initial population, which are all optimal solutions. The firefly algorithm uses the set of optimal solutions as the initial population and generates the globally optimal result. The proposed technique has experimented with the standard MCNC benchmark circuits, and the results prove that the proposed algorithm reduces the area by 3.48%, the wire length by 0.64% and the temperature by 3.33% than the best existing methodology. The proposed methodology generates a good floorplan with all the required optimization, such as area, wire length and heat generation.

A Comprehensive Review on Automation-based Sizing Techniques for Analog IC Design

Analog integrated circuits are present in most electronic systems. They must be designed carefully in order to achieve the required performance specifications. Although almost half of the design effort in a chip is spent in analog modules, there are not yet a consolidated industry of analog design automation tools capable to fully synthesize analog circuits in a fast and generic way. This is due the fact that automatic or semi-automatic design tools have to deal with high design complexity, which includes several specifications and design variables. A lot of research effort have been done in this field in the past years, proposing methods for automating parts of the design flow, from topology selection to devices sizing and layout generation. This paper presents a review of the state-of-the art in analog design automation methods, focusing on techniques and algorithms used to size robust circuits while efficiently exploring the design space.

Differentiable Constraints’ Encoding for Gradient-Based Analog Integrated Circuit Placement Optimization

Analog IC design is characterized by non-systematic re-design iterations, often requiring partial or complete layout re-design. The layout task usually starts with device placement, where the several performance figures and constraints to be met escalate its complexity immensely, and, due to the inherent tradeoffs, an “optimal” floorplan solution does not usually exist. Deep learning models are now establishing for the automation of the placement task of analog integrated circuit layout design, promising to bypass the limitations of existing approaches based on: time-consuming optimization processes with several constraints; or placement retargeting from legacy designs/templates, which rely heavily on legacy layout data. However, as the complexity of analog design cases tackled by these methodologies increases, a broader set of topological constraints must be supported to cover the different layout styles and circuit classes. Here, model-independent differentiable encodings for regularity, boundary, proximity, and symmetry island constraints are formulated for the first time in the literature, and an unsupervised loss function is used for the artificial neural network model to learn how to generate placements that follow them. The use of a deep learning model makes push-button speed placement generation possible, additionally, as only sizing data are required for its training, it discards the need to acquire legacy layouts containing insights into this vast set of, often neglected, constraints. The model is ultimately used to produce floorplans from scratch at push-button speed for real state-of-the-art analog structures, including technology nodes not used for training. A case-study comparison with a floorplan design made by a human-expert presents improvements in the fulfillment of every constraint, reaching an overall improvement of around 70%, demonstrating the approach’s value in placement design.

Simultaneous optimization of the area, wirelength and TSVs in a 3D IC design

Simultaneous optimization of the area, wirelength and TSVs in a 3D IC design

SOI radiation-hardened 300 V half-bridge date driver IC design with high dv/dt noise immunity

SOI radiation-hardened 300 V half-bridge date driver IC design with high dv/dt noise immunity

Formation of IP-Core Libraries in the User IC Design Flow for FPGAs and RSoCs

Formation of IP-Core Libraries in the User IC Design Flow for FPGAs and RSoCs

Exploiting Channel Polarization for Reliable Wide-Area Backscatter Networks

A long-standing vision of backscatter networks is to provide long-range connectivity and high-speed transmissions for batteryless Internet-of-Things (IoT). Recent years have seen major innovations in designing backscatter networks toward this goal. Yet, they either operate at a very short range, or experience extremely low throughput. This paper takes one step further towards breaking this stalemate, by presenting PolarScatter that exploits channel polarization in long-range backscatter networks. We transform backscatter channels into nearly noiseless virtual channels through channel polarization, and convey bits with extremely low error probability. Specifically, we propose a new polar code scheme that automatically adapts itself to different channel quality, and design a low-cost encoder to accommodate polar codes on resource-constrained backscatter tags. Furthermore, we devise a new metric to calculate log-likelihood ratio for accurate decoding, and present a stopping criterion of iterations to reduce decoding latency. We build a prototype PCB tag, and our experiments show that it achieves up to 11.5× throughput improvement over the state-of-the-art long-range backscatter solution. We also simulate an IC design in TSMC 65 nm LP CMOS process. Compared with traditional encoders, our encoder reduces storage overhead by three orders of magnitude, and lowers the power consumption to tens of microwatts.

Guest Editors’ Introduction: SBCCI 2021

The Symposium on ICs and Systems Design (SBCCI) is an international forum dedicated to ICs and systems design, test and EDA, held annually in Brazil. Over the past four decades, SBCCI has established itself as an important international forum for the presentation of research results on leading-edge aspects of ICs and systems, such as analog circuits, mixed-signal and digital ICs design, dedicated and reconfigurable architectures, EDA tools, design methods, embedded systems, SoC, and nanoarchitectures, as well as verification and test methods. This 34th edition of SBCCI was initially planned to take place in Campinas, 100 km from São Paulo. However, due to the continued health insecurity of the COVID-19 pandemic, it was transformed into a virtual event that took place from 23 to 27 August 2021.