High-speed Design Research Articles

Performance investigation of Ge DLTFET based digital integrated circuit

ABSTRACT The article investigates the performance of germanium source doping-less tunnel FET (Ge DLTFET)-based digital integrated circuits. For this, the compact models have been developed for DLTFETs using Verilog-A approach. Furthermore, at circuit level, the performance of Ge DLTFET is compared with its conventional counterpart silicon source DLTFET (Si DLTEFT). Two digital benchmark circuits are considered for circuit simulation such as ring oscillator (RO) and conventional six-transistor static random-access memory (6 T SRAM). The simulation results depict that the operating frequency of Ge DLTFET RO is ~ 4.48 decade higher than Si DLTFET. Similarly, the performance of Ge DLTFET SRAM cell in terms of read and write delay is much better than its conventional counterpart Si DLTFET. Hence, Ge DLTFET can be considered as a promising device structure for high-speed digital circuit design and for its applications.

Model Based Design, Prototyping and Testing of a Small Size High Speed Electrically Driven Centrifugal Pump

<div class="section abstract"><div class="htmlview paragraph">Within automotive sector, there are several high-performance applications, like, for instance, those referred to racing and motorsport, where cooling needs are usually fulfilled by simple circuits with conventional low-efficiency pumps. The cooling needs in these applications are represented by low flow rates delivered (in the range of 10 - 50 L/min). The operating conditions of these small pumps are usually characterized by very high revolution speeds, which intrinsically cause low efficiency and critical intake phenomena (cavitation) if the design is not specifically optimized to address these concerns.</div><div class="htmlview paragraph">Hence, in this paper a small-size pump operating in the racing sector has been designed using a model-based approach, built and tested having reached both high efficiency (aimed to 50%) and absence of intake operational problems (cavitation). Starting from the specific cooling request (design flow rate equal to 14.0 L/min and pressure rise equal to 2.5 bar), the very limited space available on board oriented the design to an operational revolution speed of 12000 RPM. The interest of this study was to introduce a so high revolution speed in more conventional automotive cooling pumps electrically assisted, keeping high efficiency. In fact, the strong reduction of the size of the pump allows an easy and correct positioning on board.</div><div class="htmlview paragraph">The model-based design was done by a two-steps procedure. The first made use of a 0D model which, catching main physical phenomena of the flow even in simplified form, leads to an optimum geometrical design for the impeller and the volute. A final refinement has been done with a CFD code predicting the off-design performance and limiting cavitation zones. Cavitation, which is one of the most critical issues of high-speed pumps, was completely investigated through a CFD numerical analysis.</div><div class="htmlview paragraph">The pump has been prototyped and tested on a dynamic test bench for pumps, which reproduces homologation cycles and real driving. A good agreement has been reached between theoretical and experimental results, being the mean relative error on pressure rise for all operating point close to 4 %. This model-based procedure opens the way to support the development of electric water pumps for more conventional applications (automotive, light duty engines) in which a redesign will be focused to manage the thermal state of the engine and reduce the energy absorbed during the homologation cycle.</div></div>

Analysis of Aerodynamic Characteristics of High-speed Train with Asymmetric Heads

High-speed transportation is closely related to people’s livelihood and national economy, so it becomes an important development aspect to the whole country. The safety, comfort and economy of high-speed train are the key consideration during its design process. In the future, new trains and old ones will be used for a long time, and the performance of new trains which run on the old lines may be limited. These situations make the research of high-speed train with asymmetric heads much necessary. Aiming at the feasibility of the train with asymmetric heads, the heads of train CRH3 and another typical train with a similar speed are selected. Based on the two heads, the digital models of the traditional trains with symmetric heads and the new trains with asymmetric heads are built firstly. And then their aerodynamic characteristics are computed by the SIMPLE method. In the numerical part, the performances of the trains are compared on the condition without crosswind, which shows that one of the new trains with asymmetric heads is the best among them. Moreover, the aerodynamic characteristics of this new model under crosswind is analyzed, which demonstrates that the train with asymmetric heads is feasible. The research shows that the train with asymmetric heads can achieve better results through the proper aerodynamic shape optimization design, which presents an idea for the future high-speed train design.

Retraction Note to: Memristor based high speed and low power consumption memory design using deep search method

Retraction Note to: Memristor based high speed and low power consumption memory design using deep search method

Hierarchical multipliers: A framework for high-speed multiple error detecting architectures

The demand for high-performance and reliable processing systems is steadily increasing, also in applications where multiple transient faults may occur. As multipliers are one of the main building blocks of the processing systems, employing a cost-efficient and high-speed method handling multiple-errors is of great importance. In this paper, at first a framework to achieve multiple error detection in the multipliers is proposed, which is entirely independent of the multiplier type and error detection method. Then, the self-checking hierarchical multipliers with multiple error detection capability up to the size of 64 × 64 bits are proposed in such a way that the low-cost and high-speed designs are achieved with high multiple error detection probabilities. Experimental results based on analysis and simulation show that the proposed 32 × 32 and 64 × 64 multipliers based on each of Dadda or Braum structures as high-speed parallel and array multipliers, respectively, achieve more than 99.8% error detection probability against three or more simultaneous errors. This capability for 64 × 64 multipliers is attained with 35% area overhead and less than 5% delay overhead compared to the basic non-self-checking design.

High-Speed and High-Temperature Calorimetric Solid-State Thermal Mass Flow Sensor for Aerospace Application: A Sensitivity Analysis.

A high-speed and high-temperature calorimetric solid-state thermal mass flow sensor (TMFS) design was proposed and its sensitivity to temperature and airflow speed were numerically assessed. The sensor operates at 573.15 Kelvin (300 °C), measuring speeds up to 265 m/s, and is customized to be a transducer for an aircraft Air Data System (ADS). The aim was to enhance the system reliability against ice accretion on pitot tubes’ pressure intakes, which causes the system to be inoperative and the aircraft to lose protections that ensure its safe operation. In this paper, the authors assess how the distance between heater and thermal sensors affects the overall TMFS sensitivity and how it can benefit from the inclusion of a thermal barrier between these elements. The results show that, by increasing the distance between the heater and temperature sensors from 0.1 to 0.6 mm, the sensitivity to temperature variation is improved by up to 80%, and that to airspeed variation is improved by up to 100%. In addition, adding a thermal barrier made of Parylene-N improves it even further, by nearly 6 times, for both temperature and air speed variations.

Design of High Speed, Energy, and Area Efficient Spin-Based Hybrid MTJ/CMOS and CMOS Only Approximate Adders

It is important to explore better alternatives to CMOS to sustain Moore’s law far in the future. One option is to integrate non-volatile spin devices, such as magnetic tunnel junction (MTJ), with the existing CMOS technology to augment its capability. This article presents five approximate 1 bit full adders for applications where accuracy can be traded for energy, speed, and area. The application of an approximate adder is demonstrated in image processing for smoothening an image. Three of these adders are fully non-volatile, one is partially volatile, and one is fully volatile. All the adders use SRAM-based sense amplifier (SA) to reduce sensing energy and hardware count. To reduce the delay, some of the adders utilize the parallel connection of logic devices (MTJ or MOSFET) in the logic tree. All the adders are simulated using 45 nm CMOS predictive technology model (PTM) and perpendicular magnetic anisotropy (PMA) CoFeB/MgO/CoFeB MTJ model with HSPICE simulator. After performing simulations, results show that the proposed fully non-volatile approximate adder (AXFA4) performs exceptionally well against its existing counterpart AX_MFA2 in terms of the energy-delay product (EDP) and the area-delay product (ADP) with a decrement of 84% and 80%, respectively. All the adder designs compute sum at 75% and carry at 100% accuracy, respectively.

Time jitter generation and injection algorithms for high-speed applications.

Time jitter is an important means for evaluating the performance of high-speed communication systems. Current high-speed digital designs require faster edge speeds and smaller effective data windows. Therefore, analysis of the root cause of jitter has become the key factor in determining the success or failure of a design. To analyze the jitter source of the whole link, the jitter is usually extracted and analyzed by software or hardware at the receivers. To verify the accuracy of jitter extraction at the receivers, many instrument manufacturing companies have developed oscilloscope software to inject jitter at the transmitters, but the core algorithms for jitter generation are commercially sensitive and the software cannot inject all types of jitter, particularly bounded uncorrelated jitter, into the pure signals. This paper proposes a software jitter modeling and injection algorithm that can be implemented in MATLAB and includes transmitter test signal modeling, jitter generation, and the injection of various types of jitter. Unlike other research and commercial software, the proposed algorithm enables the injection of various types of jitter, notably bounded uncorrelated jitter, into test signals. This algorithm is suitable for integration into real-time oscilloscopes for jitter generation and injection.

FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion

Optimized Field Programmable Gate Array (FPGA) implementation of Cellular Automata (CA) for high speed design requires knowledge of the platform specific logic cell architecture. In this paper, we have proposed architectures and design automation of a particular class of CA, essentially a Finite State Machine (FSM), which obey rules governed by principles of Margolus neighborhood. Under this proposition, the inputs to the next state function of the FSM for every CA cell alternates between two sets of data in every successive clock cycle. Careful choice of logic elements and their compact placement was ensured for speed-area efficient implementation. Variants of scan insertion were carried out for fault localization by properly utilizing the logic cells realizing the original Margolus CA, so that area-delay overhead is minimized. We outperform behavioral or register transfer level (RTL) based descriptions for CA implementations, expressed through conventional higher levels of abstraction, with respect to delay and occupancy count of logic slices.

Novel Radiation-Hardened High-Speed DFF Design Based on Redundant Filter and Typical Application Analysis

A cell-level radiation hardening by design (RHBD) method based on commercial processes of single event transient (SET) and single event upset (SEU) is proposed in this paper, in which new radiation-hardened D-type flip-flops (DFFs) are designed. An application-specific integrated circuit (ASIC) of a million gates level is developed based on DFFs, and SEU and single event functional interruption (SEFI) heavy-ion radiation tests are carried out. The experimental results show that the new DFF SEU ability is increased by 63 times compared with the DICE-designed DFF, and is three orders of magnitude higher than the redundantly designed DFF. The SEFI ability of the ASIC designed by the new DFF is 2.6 times higher than the circuit hardened by the TMR design.

Design and Comparative Analysis of High Speed and Low Power ALU Using RCA and Sklansky Adders for High-Performance Systems

This study examines how different initial design decisions affect the area, timing, and power of technology-mapped designs. ASIC design flow, tools used during the flow, and the factors to consider to maximize the performance and power ratio are discussed. The ALU (Arithmetic Logic Unit) is a fundamental part of all processors. In this study, two ALUs were implemented using two different types of adder circuits: a Ripple Carry Adder (RCA) and a Sklansky adder. The Cadence EDA tools were used for the implementation. A comparative analysis was conducted for the two designed ALUs in terms of area, power, and timing analysis. The ALU design was also used as an example to examine the whole workflow front-end wise by constructing a block schematic and back-end wise by floorplanning, placing, and routing the physical design.

High-Performance 32-Bit Parallel Hybrid Adder Design Using RNS and Hybrid PTL/CMOS Logic

Adders are one of the essential blocks of Arithmetic Logic Unit (ALU), addressing the memory, table indices and many more such types of applications. The speed of the adder unit more often decides the performance of CPU (Central Processing Unit) and GPU (Graphics Processing Unit) for graphics applications. The high-speed design is a very important performance parameter speed that too with less implementation area and low power consumption. In this paper, the author proposes a novel 32-bit Residue Hybrid Adder (RHA) using the Residue Number System (RNS) and implemented using a Hybrid CMOS/PTL logic style. An RNS has the advantage of representing a large integer using a set of few smaller integers to make computation more efficient and effective. On the other side, parallel prefix adders provide faster execution time as it performs the operation in parallel. With our paper, it is evident that RHA gives better performance in terms of delay, power consumption and area for arithmetic operations. The experimental analysis has been performed using the EDA tool on 45-nm CMOS technology. The power, delay and power delay product (PDP) performance parameters are compared with the existing adders and the results show that, thanks to smaller modules, proposed units have both smaller area and delay by up to 45% and 41%, and, consequently, they allow achieving up to over 46% power saving, respectively.

Energy Demand Analysis and Powertrain Design of a High-Speed Delivery Robot Using Synthetic Driving Cycles

Last mile is known as the last leg of the delivery process, which is the most expensive and time-consuming part per kilometer. The most common last mile deliveries are postal packages, groceries and take away meals. Recently, there has been a growing interest and implementation of sidewalk autonomous delivery robots. These robots travel roughly at the speed of pedestrians (6 km/h). A high-speed (15 km/h) delivery robot design is proposed for reducing the time, energy and carbon footprint of deliveries. The preliminary design of the delivery robot powertrain is based on worst-case scenario analysis and Monte Carlo simulations with synthetic driving cycles. Synthetic driving cycles were used because there are no open data available of delivery robots. Thus, the procedure presented in this paper is a general approach for cases where there is no precedent application and/or no data are available. The synthetic driving cycles are based on start and end location of food-delivery services in Helsinki, Finland. Based on the simulations, the crucial factors contributing to energy demand and its variation were analyzed. Carbon footprint of the delivered package over distance of the design is compared to existing wheeled delivery robots and quadrupeds. The motivation of the work is that showcasing the energy savings of higher speed aids government officials in their decision-making regarding delivery robot regulations. As a result of the simulations, higher operation speed lowered the energy consumption by over 40%.

High-speed permanent magnet machine multi-physics fields design for turbine application

This paper presents the multi-physics fields research of a high-speed permanent magnet machine (HSPMM) for turbine application. At first, the design considerations for the HSPMM are introduced and presented. Then, the machine electromagnetic performances are comprehensively studied with machine stator slot numbers. Moreover, the influences from the PM magnetization methods and segmentation number on PM eddy current loss reduction are further investigated. Thermal analysis is also performed for the HSPMM with the cooling water fluid volume flow rate considered. In addition, rotor strength is studied for the HSPMM with several design factors on machine rotor strength performances further studied and researched.

A Theoretical Modeling of Adaptive Mixed CNT Bundles for High-Speed VLSI Interconnect Design

The aroused quest to reduce the delay at the interconnect level is the main urge of this paper, so as to come across a configuration of carbon nanotube (CNT) bundles, namely, squarely packed bundles of mixed CNTs. The demonstrated approach in this paper makes the mixed CNT bundle adaptable to adopt for high-speed very-large-scale integration (VLSI) interconnects with technology shrinkage. To reduce the delay of the proposed configuration of the mixed CNT bundle, the behavioral change of resistance (R), inductance (L), and capacitance (C) has been observed with respect to both the width of the bundle and the diameter of the CNTs in the bundle. Consequently, the performance of the modified bundle configuration is compared with a previously developed configuration, namely, squarely packed bundles of dimorphic MWCNTs in terms of propagation delay and crosstalk delay at local-, semiglobal-, and global-level interconnects. The proposed bundle configuration is, ultimately, enacted as the better one for 32-nm and 16-nm technology nodes, and is suitable for 7-nm nodes as well.

Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

Novel Formulations of Multireflections and Their Applications to High-Speed Channel Design

Reflection theory has been long established for over decades targeted at microwave and radio frequency (RF) applications. With ultra-high-bandwidth applications emerging, such as 112 Gb/s and higher speed Ethernet protocols, discontinuities in high-speed channels negatively impact signal quality, where reflections become one of the most critical concerns in high-speed designs. In this article, for the first time, we analyzed the traditional reflection theory and proposed and verified a new formulation, which exhibits the reflection-related parameters explicitly, indicating where design optimization can be made for high-bandwidth applications using the backtracked propagation method. Our closed-form formulation is applied to high-speed channel examples, where effective mitigation of negative impact from reflections on signal integrity can be identified to be used as a prelayout channel design guide. Our proposed formulation of the reflection theory provides more accurate prediction of high-speed channel behavior to minimize the negative signal integrity impact from reflections.

An RF-SoC-Based Ultra-Wideband Chirp Synthesizer

This paper presents the design and development of a digital two-channel chirp synthesizer using a field-programmable gate array (FPGA) device. To achieve an integrated solution, the design was implemented on radio-frequency system-on-chip (RF-SoC) technology that includes digital-to-analog converters (DACs) and other radio-frequency components on-chip. To overcome the timing errors in high-speed design with DACs operating at 6.144 GHz, a memory-stitching concept was used. A prototype was developed to validate this concept by generating a baseband chirp with a bandwidth of 1.7 GHz and a sweep time of 36 μs. The synthetic chirp was upconverted to 3.5-5.7 GHz for use as the transmit signal for an ultra-wideband radar to characterize the chirp using a 1 km long optical delay line. The transmit signal was analyzed in terms of phase and amplitude errors and corrected for these errors. The root-mean-square (RMS) frequency deviation of the predistorted chirp from linearity over the 1.7 GHz bandwidth is 9.64 kHz, realizing a chirp linearity of 0.00057%. The measurement data show comparable performance of our chirp synthesizer against a commercially available arbitrary-waveform-generator (AWG) operating at a sampling rate of 60 GHz. The reported chirp synthesizer can be used in frequency-modulated continuous-wave (FM-CW) and stretch radars. Such radars are widely used for a variety of remote sensing measurements.

Mm-Wave Complex Permittivity Extraction of LTCC Substrate Under the Influence of Surface Roughness

As many emerging technologies require the use of high-speed signals, the understanding of dielectric properties of materials used in manufacturing printed circuit boards (PCBs) is an essential aspect for accurate high-speed circuit designs, especially at millimeter-wave (mm-wave) frequencies. This work demonstrates a methodology for extracting complex relative permittivity of dielectric substrates covering mm-wave frequencies. For this purpose, low-temperature cofired ceramic (LTCC) substrate was measured up to 85 GHz and its complex relative permittivity was extracted. The approach used in this work is based on multiline thru–reflect–line (TRL) calibration for measuring the propagation constant and electromagnetic (EM) simulations to estimate the losses contributed by the conductor while accounting for surface roughness. An estimate of complex relative effective permittivity is obtained, from which the actual relative dielectric constant and the loss tangent of LTCC substrate are extracted. The estimated values for the relative dielectric constant and the loss tangent show an excellent agreement compared with the results obtained via split cavity resonator measurements.

Analysis of Several Electromagnetic Band Gap Topologies for Reducing Simultaneous Switching Noise

In the case of high-speed PCB design, the use of electromagnetic band gap (EBG) structure technology is useful in reducing simultaneous switching noise (SSN) in high-frequency applications. In high-frequency processes, parasitic filters are ineffective. Conducted emission is reduced by including the planar EBG structure into PCB plane layers. Various planar structures are taken and simulated in this research, including LC type, Z-Bridge with embedded double square, L-Bridge with slit type, alternating impedance, slit type EBG, Triple square type, and two topology type structures. A frequency sweep of 0 GHz to 10 GHz is used with a FEM solution. Theoretical calculations of the structures are performed and compared to simulation results, which show that they are very similar. Based on the best bandwidth and noise depth, the L-Bridge with slit and Triple square type cases were chosen, constructed, and analyzed using a vector network analyzer; it was discovered that the noise depth and bandwidth are in good accord. In addition, the AC analysis-Electric Field distribution for power and ground planes is explored, and the maximum and minimum field levels may be understood as a consequence.