FinFET Design Research Articles

Design and Implementation of FinFET and GnrFET Based Dynamic Path Auto Configurable Joint Adder Subtractors

Design and Implementation of FinFET and GnrFET Based Dynamic Path Auto Configurable Joint Adder Subtractors

Research of Gate-All-Around Field-Effect Transistors

This report provides an overview of GAA FETs also known as Gate-All-Around FETs, focusing on their introduction and limitations, based on a comprehensive review of current literature and online resources. GAA FETs represent an evolution of FinFET technology, which itself was developed from traditional MOSFET designs. Each iteration has aimed to improve performance and overcome limitations of its predecessor. The GAA architecture offers superior electrostatic control, resulting in higher drive currents, reduced leakage, and improved subthreshold swing, making it ideal for high-performance, low-power applications. Despite these advantages, GAA FETs still face challenges with short-channel effects (SCEs) as device dimensions shrink. Gate-All-Around (GAA) is a transistor architecture designed to address the limitations of the FinFET design. Unlike FinFET, where the channel is surrounded on three sides by the gate, GAA surrounds the channel on all four sides by turning the FinFET structure sideways, making the channels horizontal. This design provides enhanced control over the transistor switch. The fabrication of GAA transistors involves a series of highly precise processes, which enable improved transistor scaling with reduced variability, resulting in increased performance and lower power consumption.

Design of high-K dielectric HSS-DMG Junctionless FinFET using hetero GOS for nanoscale application

This article presents a detailed investigation of the High-K dielectric horizontal stack spacer (HSS) dual material gate junction-less FinFET device for analog and RF application using the gate oxide stack (GOS) approach. At first, the impact of the horizontal stack spacer (HSS) with different high-K spacer materials are investigated by placing different dielectric material like HfO2, SiO2, Si3N4, and TiO2 on the horizontal spacer. The simulation results of the device indicate that the High-K dielectric HSS makes the device high stability toward the leakage current and static power dissipation at the sub-nano scale regime. The DC characteristics of the device are also investigated alongside the AC/RF characteristics. The proposed device predominantly improves performance in terms of parameters like subthreshold swing, Ion/Ioff, and DIBL. The proposed device shows a high ON current of 8.56 × 10−5 A μm−1, which is about 15% higher than the existing literature, and the device also makes a notable impact on the leakage current by restricting it to 9.635 × 10−12 A/μm. The simulation of the device is carried out with optimization of the doping to investigate and improve the device’s performance. The device shows an excellent improvement in performance which is highly suitable for future-ready device applications.

Challenges for Leading Edge node FINFET

The primary focus of this work is to find out the challenges associated with 7nm node finFET. To enable the current generation of gadgets/instruments, foundries are going toward smaller geometries (FinFET 7nm, 5nm, etc.) for manufacturing SOC/ASIC. To support the 7nm technology node without EUV, the Layout Design Rules have been scaled quite aggressively. As a result, obtaining satisfactory performance and yield in High Volume Manufacturing (HVM) has become a difficult undertaking. The gains in terms of power, performance, and other characteristics that become available with reduced geometries are the main drivers driving this movement. Analog/mixed-signal circuits, on the other hand, do not fully achieve these gains. They get increasingly difficult to design, with higher parasitic resistance and capacitance, more layout-dependent effects, and, in certain cases, layout growth. While in terms of fabrication the challenges are in node and cost, mask making, patterning, transistor formation, BEOL, MEOL, Technology parasitic elements and process control etc. This indicate what are the challenges for design of 7nm node FinFET.

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Improved Performance Analysis and Design of Dual Metal Gate FinFET for Low Power Digital Applications

Impact of PVT Variations on Optimizing Silicon Power

The scaling of CMOS technology faces challenges as the demand rises, but FinFETs emerging as a vital alternative for 22nm technology node and lower. Otherwise, FinFETs tend to have multiple PVT variations, making static timing analysis (STA) more flexible and suitable to analyze the timing delay of the logic generation. Device simulation and statistical temporal analysis are used to derive PVT variation models for FinFET-based standard cell designs. Mixing different FinFET design styles shows promise in optimizing delays and leakage, as FinFETs offer better control of short-channel effects and processing scalability. Furthermore, lowering clock skew is also a prime design aspect to consider. However, as technology scales to smaller devices, process, voltage, and temperature (PVT) variations make minimizing clock distortion very difficult. To mitigate the effects of PVT variations, many previous works proposed a Post Silicon Tuning (PST) architecture to dynamically balance the skew of the clock tree. In this paper, we will disclose the details of clock tree synthesis optimizations and FinFET logic developments minimizing PVT variations.

High-breakdown-voltage GaN-based vertical FinFET design

High-breakdown-voltage GaN-based vertical FinFET design

Design and Comparative Analysis of FD-SOI FinFET with Dual-dielectric Spacers for High Speed Switching Applications

Design and Comparative Analysis of FD-SOI FinFET with Dual-dielectric Spacers for High Speed Switching Applications

Design of Dual-Material Gate Junctionless FinFET based on the Properties of Materials Forming Gate Electrode

This work elaborately investigates the electrical behaviour and short channel performance of Dual-Material Gate Junctionless Fin Field Effect Transistors (DMG-JLFinFETs) with multiple-gate metal pairs and varying gate metal length ratios. Rigorous analysis on the nature of DMG-JLFinFET with gate length as low as 10 nm is done using a device simulator by Silvaco, Inc. The gate material closer to the source, namely M1, has a dominating influence on the threshold voltage (V th) and tunnelling current (I tunn) than the gate material closer to the drain (named M2) in a DMG-JLFinFET. I tunn is lower when the work function of M1 (Φ M1) is greater than the work function of M2 (Φ M2). The relative change in threshold voltage is minimum for Platinum–Gold (PtAu)-DMG-JLFinFET (0.68%). Titanium–Aluminium (TiAl) and Nickel–Titanium (NiTi) gate material pairs, having the same work function difference of 0.38 eV, have the least Drain-Induced Barrier Lowering (DIBL) of 12.88 mV/V. A better Sub-threshold Swing (SS) is observed for DMG-JLFinFET having Φ M1 < Φ M2. For devices with Φ M1 > Φ M2, SS can be improved by making a length of M1 (L M1) greater than 70% of the total gate length (L g).

SOI FinFET Design Optimization for Radiation Hardening and Performance Enhancement

This work proposes Total Ionizing Dose (TID) hardening techniques compatible with conventional 14-nm-node silicon-on-insulator (SOI) FinFETsf process flows through performing 3-dimensional (3-D) simulations based on technology computer-aided design (TCAD) tools. The simulation results reveal a significantly critical TID impact induced by trapped charges in the buried oxide (BOX) and the spacer with calibration against 14 nm SOI FinFETfs experimental data (error < 6%). Inspired by the physical interpretation, an optimization technique featuring an optimized gate structure, spacer length, and substrate bias is designed. The optimized gate structure is utilized to enhance the local gate-to-channel coupling at the bottom and reduce the generation and capture of electron-hole pairs. By reducing the spacer length, a lower sensitive volume in the spacer can effectively suppress the TID response. The setting of the negative substrate bias greatly improves the subthreshold characteristics, weakening the TID effect in the BOX. By adopting the combined optimization including these techniques, the threshold voltage shift (VTH) induced by a 5 Mrad(SiO2) irradiation can be reduced to 21 mV, whereas VTH is 45 mV with only gate structure optimized and 97 mV without hardening. Meanwhile, the ION/IOFF after radiation increases to 1 × 107, which is at least four orders of magnitude better than the original device. Meanwhile, subthreshold swing (SS) is reduced from 81 mV/dec to 71 mV/dec, and Drain Induced Barrier Lowering (DIBL) is reduced from 120 mV/V to 99 mV/V, respectively. The combined optimization design is demonstrated as an effective method to improve the tolerance against TID irradiation without compromising performance, promoting 14 nm SOI FinFET’s application in future harsh space environments.

A Novel Design of Low Power & High Speed FinFET Based Binary and Ternary SRAM and 4*4 SRAM Array

The Conventional Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOSFET) design techniques have limitations in designing the Integrated Circuit (ICs), especially with memories of multiple valued logic (MVL) in nanotechnologies. FinFET technologies provide the possibilities of low logic gates and small chip areas with high speed. Memories play an essential role in all types of devices. This paper aims to optimize the power and increase the speed of the SRAM Cell and Array using different techniques in 18nm FinFET technology. The presence of a ternary input provides an additional degree of freedom for the operation of the memory cell. The SRAM cells are also implemented at a Quantum level to improve the results in terms of area, energy, and speed. Simulation and Analysis of the design is done using Cadence Virtuoso Analog Design Environment Tool and Quantum Dot Cellular Automata Designer Tool. The proposed Multi-Threshold Complementary MOS (MTCMOS) based SRAM Array design exhibits an improvement of 4.56% in power consumption and 19.29% in speed as compared to a Conventional CMOS SRAM Array. The proposed ternary implementation of the MTCMOS-based SRAM cell is found to have a 24.9% reduction in power consumption and a 39% improvement in speed as compared to the proposed conventional ternary CMOS SRAM array while SRAM cell latency is 1 clock cycle. It occupies an area of 0.04 µm2 and consists of 33 quantum cells. The average energy dissipation of this SRAM cell is found to be 40% better than the latest existing literature for the design.

Design and Characterization of a Novel FinFET based NCL Cell Library for High Performance Asynchronous Circuits

In recent times, synchronous circuits are facing design related issues like clock skew, glitch power, EMI, leakage power, etc. The clock-less design paradigm – Asynchronous design challenges most of these issues and accepted as a better alternative to clocked circuits. QDI based Null Convention Logic (NCL) is such a clock-less design concept. However, NCL designs couldn’t get wide spread acceptance due to unavailability of commercial CAD tools and design compatible NCL standard cell library. The proposed research work in this paper demonstrates design and characterization of FinFET based NCL cell library to facilitate QDI based asynchronous circuit design. The NCL cells are designed with ASAP 7nm PDK. A complete set of 27 NCL threshold gates are developed and characterized in cadence using ocean scripting. Various time and energy models are extracted for different process corners using EDA platform. The proposed work will help research scholars to implement NCL based asynchronous circuits. This paper also demonstrates comparative performance analysis of bulk-CMOS and multi-gate FinFET based NCL threshold gates in 16 nanometer technology. The analysis has concluded average 19% of improvement in power-delay produce for FinFET based cells compared to its CMOS counterparts. To showcase two-dimensional comparison, various static and semi-static NCL gate structures are also compared in term of their power and speed. Various arithmetic circuits are designed using these standard NCL cells to demonstrate its application. The results indicated substantial performance improvement in terms of power and speed.

Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell

Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

Design and Performance Optimization of Junctionless Bottom Spacer FinFET for Digital/Analog/RF Applications at Sub-5nm Technology Node

This article for the first time reports the design and performance optimization of Junctionless (JL) Bottom spacer (BSP) FinFET. Initially to get the desired value of workfunction () and fin thickness (Tfin) for analog/RF analysis, the optimization of these parameters has been done by considering several values. It has been noticed that the increase in and reduction in Tfin can lead to better electrical performance with suppressed short channel effects (SCE). Further, it is also observed that reduction in bottom spacer height (HBSP) can fetch enhanced analog/RF performance considering the improvement noticed in transconductance (gm), intrinsic gain (AV), transconductance generation factor (TGF), cutoff frequency (fT), and Gain frequency product (GFP). Moreover, when the bottom spacer dielectric permittivity (KBSP) is increased from 3.9 to 22, it has been found that the analog/RF performance degrades significantly.

Design of FinFET based low power, high speed hybrid decoder for SRAM

This paper proposes a novel FinFET based hybrid logic design for line decoders, which comprises of transmission gate logic (TGL), modified gate diffusion input (MGDI) logic and conventional NAND based FinFET logic. The 2–4 FinFET based decoder is designed using two topologies: (i) a 14- transistor topology for low power dissipation and lesser area and (ii) a 15-transitor topology for high-speed performance. Using the two topologies mentioned above, both inverting and non-inverting decoders of size 2–4 and 4–16 are designed. SPICE simulations of the proposed decoders are done at 45 nm CMOS and FinFET technologies and compared with different logic styles such as conventional logic, MGDI, mixed logic, and mixed MGDI logic at different frequencies with varying supply voltages and the proposed design outperforms other logic styles compared. The proposed FinFET hybrid decoder exhibits 6% and 77% lower power; 11.6% and 61.26% lower delay; 17% and 91.10% lower PDP respectively compared to the FinFET mixed decoder and CMOS hybrid decoder.

DC and RF performance of lateral AlGaN/GaN FinFET with ultrathin gate dielectric

In this study, an enhancement-mode (E-mode) GaN high electron mobility transistor (HEMT) with lateral tri-gate structure field effect transistor (FinFET) is proposed. To passivate the fin width, while keeping the normally-off performance of the FinFET intact, an ultrathin aluminium-oxide/sapphire (Al2O3) gate dielectric is proposed (in a basic single-finger 0.125 mm device). Later, the DC and radio frequency (RF) performances of the proposed FinFET designs (with optimized fin width and Al2O3 thickness) are compared with that of conventional planar HEMT. DC and RF measurements are performed using power transistors in ten-fingers configuration, with a total gate periphery of 2.5 mm. The effect of Fin structure and Al2O3 thickness on the electrical performance of HEMTs, including threshold voltage (V th) shift, transconductance (g m) linearity, small-signal gain, cut off frequency (f t), output power (P out), and power-added efficiency (PAE) are investigated. Based on our findings, FinFET configuration imposes normally-off functionality with a V, while the planar architecture has a V. Originating from passivation property of the alumina layer, the FinFET design exhibits two orders of magnitude smaller drain and gate leakage currents compared to the planar case. Moreover, large signal RF measurements reveals an improved P out density by over 50% compared to planar device, attributed to reduced thermal resistance in FinFETs stemming from additional lateral heat spreading of sidewall gates. Owing to its superior DC and RF performance, the proposed FinFET design with ultrathin gate dielectric could bear the potential of reliable operating for microwave power applications, by further scaling of the gate length.

Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects

Design of DG FinFET based driver circuits for energy efficient sub threshold global interconnects

Design of Sub-40nm FinFET Based Label Free Biosensor

Design of Sub-40nm FinFET Based Label Free Biosensor

Booth Multiplier Based on Low Power High Speed Full Adder With Fin_FET Technology

This paper proposes a novel Fin FET-based HSFA for the multiplier in order to overcome the issues of low speed operation. It is advantageous to use Fin FETs to construct the arithmetic circuit while assessing the available works. The carry propagation and slow operation of the old technique are disadvantages. The CMOS-based compressor circuit, on the other hand, suffers from leakage current, which reduces its driving capabilities. High current DSP applications are well matched to the design's specifications. Even with a supply voltage of 1 volt, the proposed device has a decent driving capability. As a result, the circuit runs more quickly and has less latency. A transmission gate is used in the design of the suggested adder structure to selectively block or transfer data from the input to output. Half adder and adder are shown in the following illustrations. The smaller the transistor count, the less power it uses. The suggested Fin FET design for the smaller transistors has a superior driving capability than the CMOS equivalent. Additionally, when cascading, the Fin FET based adder may contribute to superior switch performance, such as when using ripple carry adder. There is also the possibility of a low operation, which may operate at Low wattage Electronic designs for high-performance and small devices have become increasingly dependent on the use of VLSI circuits. The power of a processor is determined in large part by the multiplier used in its design. Multiplier factor booth coding is being used to reorder the input bits in order to reduce facility use. The booth decoder works by rearranging the specified booth equivalent. The Booth decoder has the ability to expand the range of zeros. As a result, the power consumption of the design will be decreased even more. As soon as the input bit constant drops below zero, related rows or columns of an adder must be disabled, if possible.

Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node

Design and Optimization of Dual Material Gate Junctionless FinFET Using Dimensional Effect, Gate Oxide and Workfunction Engineering at 7 nm Technology Node