Fabrication Process Design Research Articles

Ab initio design of fabrication process and shape control of self‐organized Tera‐bit‐density nano‐magnets in dilute magnetic semiconductors by two‐dimensional spinodal decomposition

A new fabrication process in a bottom-up nanotechnology to realize self-organized Tera-bit-density nanomagnets is designed based on ab initio calculations of the effective pair interactions between magnetic impurities in dilute magnetic semiconductors (DMS) and on Monte Carlo simulation of layer-by-layer crystal growth. We show that growth positions, shape and density of quasi-one-dimensional nano-magnets in the DMS can be controlled by the nano-scale seeding on the semiconductor substrate and the vapor pressure or concentration of the doped magnetic impurities under the thermal non-equilibrium crystal growth condition, such as molecular-beam epitaxy, metal-organic vapor phase epitaxy or metal-organic chemical vapor deposition. (© 2006 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Hole-type two-dimensional photonic crystal fabricated in silicon on insulator wafers

We report the realization of two-dimensional (2D) photonic crystal (PhC) holes array using synthesized processing techniques of deep UV lithography, time-multiplexed reactive ion etching (TMRIE) and focus ion beam (FIB) etching. In this study, mixed density of holes and waveguide patterns of 2D PhC structures was first formed in silicon on insulator wafers through use of a scanner. Ultra wide grooves were then defined, aligned to the deep submicron size devices. Following deep etching of more than 50 μm by TMRIE, PhC structures were then revealed for device etching. Such design of fabrication process allows realization of disparate pattern dimensions and also etching depths. Through avoidance of etch lag effect, notching of devices at interface of device silicon and buried oxide layer was avoided. At the same time, through a singular FIB etch in the final step of the process following buried oxide release for PhC structures on critical dimension structures, severe loading effects of such structures were avoided to enable a wide process window of lithography and etch.

Synthesized processing techniques for monolithic integration of nanometer-scale hole type photonic band gap crystal with micrometer-scale microelectromechanical structures

This article reports the synthesized fabrication process design and module development that enabled the monolithic integration of deep submicrometer size, two dimensional hole-type photonic band gap crystals (PhCs) with microelectromechanical system (MEMS) actuators and optical testing structures (OTS). Techniques enabling sublithographic wavelength patterning using only conventional chrome-on-glass binary photomasks without phase shift features were achieved through the manipulation of mask bias designs and the partial coherence control of the lithographic exposure system. Together with the development of time multiplexed reactive ion etching and focus ion beam milling techniques, such design of the process allows the realization of highly dense PhC and MEMS actuators physically released from the buried oxide layer. Here, disparate pattern dimensions [with PhC critical dimensions (CDs) of only 175nm, MEMS typical dimensions of 2μm, and OTS openings more than 400μm wide], varied etch depth (3μm for the PhC and MEMS, 61μm for the OTS), and the requirement of a sufficient process latitude for exposure and etch processes are some of the key challenges that were overcome for a successful integration of air-bridge-type PhC CDs with movable MEMS actuators. Hence, the works described in this article enable MEMS tunable PhC properties with potential application in next generation dynamic optical communication networks and photonic integrated circuits.

Design and fabrication of novel three-dimensional multi-electrode array using SOI wafer

A novel method has been developed for the manufacture of a three-dimensional multi-electrode array (3D MEA), particularly, the shape of micro-tips can be varied by MEMS technology to construct different multi-electrode array. It improved the disadvantage of single electrode, which meant that it was available for multi-recording and analysis of a series of signals. Overcoming the difficulty of making interconnection line on 3D MEA chips via innovative fabrication process design. Using local isolation and removal of oxide films to forming electrodes and interconnections with oxide isolation covers. A 10 × 10 3D MEA with a distance of 100 μm between each other for further bio-neural signals was demonstrated, and a test on rabbit retina was also available. Besides, integrating pre-amplifier and built-in resistors with 3D MEA was brought out to hopefully increase the efficiency of sensing.

Epoxy resins as stamps for hot embossing of microstructures and microfluidic channels

Fabrication of micro total analysis systems using plastic substrates has become more prevalent in the recent literature with the driving force being the development of inexpensive disposable analytical devices. Hot embossing is one polymer micro-fabrication method that has shown significant promise in this area because identical polymeric devices can be produced using a master to repeatedly stamp an image into a number of plastic substrates/materials. One major disadvantage of hot embossing in a research setting is the time and expense needed to produce a stamping tool able to withstand the temperature and stress of the embossing process. This paper describes a method of producing an epoxy stamp that is relatively inexpensive, rapid to produce and durable enough to withstand multiple embossing cycles ( n > 50). The epoxy-stamping tool can be micro-molded from either a positive or a negative imaged master and is compatible with a number of materials including SU-8 resist on silicon, PDMS or glass. The low viscosity of the pre-cured epoxy permits the reproduction of microstructures with dimensions below 1 μm in size and allows for the transfer of these small structures to PMMA by hot embossing without loss in detail. The stamp fabrication process can be performed in less than 4 h. When the process is combined with rapid device prototyping capabilities of SU-8/silicon micro-fabrication the entire process of microchip fabrication process (design to device) may be completed in 24–48 h.

Dc and un SQUID's for readout of ac-biased transition-edge sensors

We have developed a set of SQUIDs optimized for readout of ac-biased transition edge sensors. Junction shunts are made of Pd and attached to cooling fins to facilitate low-noise operation at sub-kelvin temperatures. SQUID's have a low loop inductance in order to reach a large natural dynamic range even without negative feedback. The SQUIDs are intended to be used for frequency-domain multiplexing of X-ray calorimeter arrays. Both traditional dc-SQUIDs and novel un-SQUIDs are manufactured. The fabrication process and SQUID design criteria are reviewed.

Residual stress and fracture in thick tetraethylorthosilicate (TEOS) and silane-based PECVD oxide films

This paper reports residual stress measurements and fracture analysis in thick tetraethylorthosilicate (TEOS) and silane-based plasma enhanced chemical vapor deposition (PECVD) oxide films. The measured residual stress depended strongly on thermal process parameters; dissolved hydrogen gases played an important role in governing intrinsic stress. The tendency to form cracks was found to be a strong function of film thickness and annealing temperature. Critical cracking temperature was predicted using mixed mode fracture mechanics, and the predictions provide a reasonable match to experimental observations. Finally, engineering solutions were demonstrated to overcome the problems caused by wafer bow and film cracks. The results of this study should be able to provide important insights for the design of fabrication processes for MEMS devices requiring high temperature processing of films.

Modeling superconducting components based on the fabrication process and layout dimensions

A procedure is described where the mask dimensions of superconducting components are used in SPICE simulations to predict the performance of a device. Thickness tolerances of the fabrication process, as well as mask bias offsets and mask tolerances are included in the component models. This makes it possible to predict circuit yield by Monte Carlo analyses, which are based on the fabrication process design rules. Model descriptions of all the components used in a standard superconductor multilayer process are given, and the accuracy of the models are verified. The superconducting components that are modeled include microstrip transmission lines, coupled transmission lines, resistors and Josephson junctions. The usefulness of this procedure is demonstrated by simulation results of a stack amplifier, where the yield of the circuit is calculated for the lumped element model and the proposed model, which includes parasitic elements.

A methodology for concurrent process-circuit optimization

In order to optimize integrated circuit designs, it is critical not only for circuit designers to adjust circuit geometries but also for process developers to adjust device characteristics for optimal overall system performance. This paper describes concurrent process-circuit optimization (CPCO), a methodology for concurrent integrated circuit optimization that spans the fabrication process design and circuit design disciplines. CPCO enables process developers and circuit designers to work coordinately toward the common goal of optimizing a system-level objective, and therefore produces better designs than single-discipline optimization schemes. The methodology logically partitions the overall integrated circuit optimization task into loosely coupled process and circuit design tasks that may proceed concurrently-this produces substantial time savings over a flat all-at-once optimization approach. Finally, the CPCO method formulates a multiobjective optimization problem that may be used to negotiate tradeoffs in adjusting a single process to optimize multiple circuits, to optimize nominal circuit performances or to improve circuit yield. The implementation of the CPCO method in an extensible object-oriented software architecture is described. Results of applying the methodology to integrated circuit design examples with industrial grade simulation tools are presented. The results demonstrate substantial performance gains over separate process/circuit optimization and substantial time savings over all-at-once combined optimization.

Design and fabrication of submerged cylindrical laminates—I

This is the first of a two-part paper concerned with both structural and fabrication process design of a closed-end laminated composite cylinder intended for service in deep sea environment. The cylinder is made of many different orthotropic layers and is loaded by uniform, axisymmetric surface tractions. In addition, piecewise uniform eigenstrains and residual stresses may be caused in the layers during fabrication, by fiber prestress for waviness reduction and by piecewise uniform changes in temperature. The overall goal is to assure efficient use of the composite structure under a prescribed hydrostatic pressure, and to select fiber prestress distribution such that the total stresses in the plies do not exceed certain strength magnitudes. Mechanical and residual stresses in the layers are evaluated with mechanical and transformation influence functions. For the proportional loading applied by a hydrostatic pressure, a procedure is outlined for design of several layups such that the cylinder wall experiences an isotropic in-plane strain and, therefore, all layers support the same compressive normal stresses, regardless of fiber orientation. The results are applied in design and analysis stress fields in a specific structure. Fabrication process design is discussed in the second part of the paper ( Srinivas et al., 1999, Int. J. Solids Structures, 36, 3945–3976) .

High-yield processing and single-mode operation of passive antiguide region vertical-cavity lasers

We report the first continuous-wave (CW) operation single-mode, low-threshold, passive antiguide region (PAR) vertical-cavity surface-emitting laser (VCSEL) using organometallic chemical vapor deposition (OMCVD) for the regrowth of the PAR structure. With improved laser wafer design, fabrication process and regrowth design, a stable single fundamental mode at high currents has been achieved experimentally for laser aperture as large as 16 /spl mu/m diameter. Single-mode power of 1.7 mW is achieved with more than 20-dB high-order mode suppression. The lasers show a more than 99% yield with high uniformity. Isolation etch and wet-thermal oxidation are used to study and eliminate the finite-leakage current in the PAR VCSEL's. Using multimode rate equations in conjunction with beam propagation method, single-mode lasing criteria is derived for PAR VCSEL. PAR VCSEL is shown to be a very efficient structure to meet the single-mode lasing condition.

An accurate HJFET capacitance-voltage model for implementation with a circuit simulator

We present a new accurate HJFET capacitance model to implement with a circuit simulator. This is an analytical model that describes capacitance-voltage (C-V) characteristics over a wide supply voltage range. The model for a capacitance component due to two-dimensional electron gas (2-DEG) conduction is based on gradual channel approximation, and takes into account the gradual capacitance transition near the threshold voltage. It also takes into account the field dependence of the 2-DEG mobility, which is very strong for deep sub-micron devices. The model for parasitic MESFET capacitance is based on the formula for a Schottky diode. Since the model consists of physical parameters, it provides feedback between the fabrication process and circuit design. The simulated results agree well with the measurements.

Causal modelling of semiconductor fabrication

Semiconductor fabrication is the manufacturing process by which wafers of silicon are turned into integrated circuits. Reasoning about how wafers are affected by fabrication operations is an important aspect in getting computers to aid in the diagnosis of manufacturing faults and in the design of new fabrication processes. Our research has been aimed at characterizing the knowledge needed to construct qualitative, causal models that can support diagnosis and design of the processes by which semiconductors are manufactured. This article presents our models of wafer structure and the operations that are used in semiconductor fabrication, and describes how a domain-independent simulator uses these models to determine how the operations affect the wafer structure. We also demonstrate how the causal dependencies recorded by the simulator can be used to diagnose manufacturing faults. We conclude with a comparison of our method of using discrete, causal models to other methods of modelling semiconductor fabrication.

Diffusion coefficients of Pb in AgPb determined by surface segregation studies

Due to experimental issues, atomic transport kinetics in nanostructures is still rarely quantitatively investigated despite its significant importance for the design of nanostructure fabrication processes and the prediction of nanoobject structure and physical property ageing. Atomic diffusion in nanostructures is expected to be mainly mediated via atomic transport in interfaces. However, in order to fully understand atomic transport in nanostructures, it is necessary to develop experimental methods allowing for the measurement of diffusion coefficients in nanovolumes, in interfaces, and in interface intersections. To date, this type of measurement has been essentially performed in nanocrystalline materials, giving access to diffusion measurements in nanocrystals corresponding to the nanograins, in grain boundaries corresponding to the interfaces between disoriented crystals of same nature, and in triple junctions corresponding to the grain boundary intersections. This chapter presents the current methods and techniques reported in the literature that have been used for such a type of measurement. Some of the original observations concerning atomic transport in nanocrystalline materials are also presented and discussed.

Automatic Rheological Measurement and Processing Calculations

This paper describes an automatic extrusion rheometer that will provide some of the polymer melt rheology data needed in the design of fabrication processes. The data are processed and stored in a computer, and as an example the computer is used to predict the parison dimensions in a blow moulding process. The predictions are compared with practical observations.