Design Of Doherty Power Amplifier Research Articles

Design of Doherty power amplifier with power back-off extension based on harmonic tuning and output combining network optimization

This paper proposes a Doherty power amplifier (DPA) design method based on harmonic tuning and output combining network (OCN) optimization to extend the power back-off (PBO) range. Firstly, based on the optimal harmonic load impedance, a harmonic tuning optimization method is used to design the harmonic tuning network of the amplifiers, effectively improving the efficiency at saturation and PBO. Secondly, the fundamental output matching network and the post-matching network are considered as an OCN. The S-parameters of the OCN are calculated and utilized in the DPA design. To further expand the PBO range, the carrier load impedance at PBO is determined by considering the relationship between PBO range and reflection coefficient. Finally, a multi-objective evolutionary algorithm combined with the theory of solution set is used to optimize the OCN design, simplifying the design process of the output matching network. For verification, a high-efficiency DPA operating at 1.68 GHz with a large PBO range of 9.5 dB is designed and measured. Results indicate that the proposed DPA achieves a saturated output power greater than 44 dBm, with a peak efficiency of up to 75.2%. The efficiencies are 68.5% and 61.0% at 6 and 9.5 dB back-off powers, respectively.

Broadband dual-input doherty power amplifier design based on a simple adaptive power dividing ratio function

Broadband dual-input doherty power amplifier design based on a simple adaptive power dividing ratio function

Asymmetric Doherty power amplifier design considering the effects of peaking power amplifier early conduction

During the design of a Doherty power amplifier (DPA), the phenomenon of peaking PA turning on in advance is commonly observed. This is mainly due to the feedback of the main PA signal to the gate of the peaking PA through the gate-drain feedback capacitor, which results in an increase in its gate voltage. As a result, the overall efficiency of the back-off region is significantly reduced. This paper first describes the phenomenon of peaking PA turning on in advance. The formula for the voltage (referred to as the feedback gate voltage, FGV) imposed on the gate of the peaking PA by the main PA signal is then deduced. On this basis, the FGV is analysed numerically. For verification, an asymmetric DPA with a 9 dB output back-off (OBO) power level is designed and fabricated in this paper using GaN CGH40010F and CGH40025F transistors. According to the measurement results, the saturated drain efficiency of the DPA is 53.5%–63.3% in the 0.75–1.25 GHz band, the efficiency at the 9 dB OBO level is between 45.5%–54%, and the saturated output power is between 45 dBm–45.7 dBm, with a saturation gain of more than 8 dB.

Design of Broadband Doherty Power Amplifier Based on Misaligned Current Phase

A broadband Doherty power amplifier (DPA) always experiences an efficiency degradation between two efficiency peaks, especially at two side bands. In this study, the efficiency degradation was demonstrated to be caused caused by the in-phase power combining at the saturation power level. To solve this problem, current misalignment was introduced into the broadband DPA design. The carrier and peaking PA have different current phases when performing the power combination at the saturation power level. In this work, it was also demonstrated that the efficiency in the high-power region of a DPA can be improved by elaborately using misaligned current phases. A detailed analysis and the design procedure of a broadband DPA are presented in this paper. And a 1.5–2.45 GHz broadband DPA was implemented and measured. The fabricated DPA achieves a saturation output power of 42.7–44.9 dBm, a saturation drain efficiency (DE) of 62.7–74.1% and a gain of 10.2–13.9 dB over 1.5–2.45 GHz. Moreover, the fabricated DPA also achieves a 6 dB back-off DE of more than 49.1% in the frequency band of interest.

Automatic multi‐objective particle swarm optimization method for effective Doherty power amplifier design

AbstractIn this paper, an automatic multi‐objective particle swarm optimization (AMOPSO) method is developed for the design of Doherty power amplifiers (DPAs). In comparison to the well‐known built‐in optimizer available in commercial simulators, the proposed method not only reduces the optimization time, but also provides superior power added efficiency (PAE) for the final power amplifier. According to the reported measurements, the output PAE of the fabricated DPA exceeds 50% at 6 dB backoff, the saturated PAE is more than 61%, and the saturated output power (Pout) is over 43 dBm in the target frequency range of 1.9–2.1 GHz. As compared with existing optimization methods, the proposed method allows reducing optimization time by more than 37%.

Simplified Emulation of Active Load Modulation for a Millimeter-Wave GaN MMIC Doherty Power Amplifier Design

Based on large-signal simulations, this article proposes a simplified method to emulate the active load modulation between the carrier and peaking transistors in a Doherty power amplifier (DPA) design. In contrast to the conventional load–pull method, the proposed method contributes to emulating the active load modulation between the load-modulated transistors with considering their nonlinear interaction. It offers the advantages of predicting the real-world performance of the load-modulated transistors and providing the optimum load-modulation trajectories to be synthesized in a DPA design. To verify the proposed method, a two-way millimeter-wave (mmWave) gallium nitride (GaN) microwave monolithic integrated circuit (MMIC) DPA is designed from 25.5 to 27 GHz. The measured results show that the realized MMIC DPA achieves power-added efficiency (PAE) higher than 30% at saturation, 27% at 6-dB back-off, and 21.5% at 8-dB back-off, with a saturated output power higher than 31.4 dBm across the band. When tested using a 400-MHz modulated signal with digital predistortion (DPD), the MMIC DPA shows adjacent channel power ratio (ACPR) levels better than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 40 dBc over the band.

Theory and Design of Doherty Power Amplifier With Active Harmonic Injection

Theory and Design of Doherty Power Amplifier With Active Harmonic Injection

A Dual Load-Modulated Doherty Power Amplifier Design Method for Improving Power Back-Off Efficiency.

In this paper, the load modulation process of a Doherty power amplifier (DPA) is analyzed to address the issue of why designed DPAs have a very low efficiency in the back-off state in some cases. A general formula of the real load modulation process is also given for analyzing the load modulation of a peak PA matching network. This provides a new perspective for improving the back-off efficiency of a DPA. To improve the power back-off efficiency of a DPA, a dual load-modulated DPA (D-DPA) design method is proposed. The core principle of the proposed design method is to control the load modulation process from the carrier PA to the peaking PA based on the design method of the traditional two-way DPA. The efficiency of the peaking PA in the back-off region is enhanced, thereby improving the efficiency in the entire back-off region of the DPA. Based on the proposed design method, a D-DPA operating at 2 GHz is designed and fabricated. The test results show that the saturated output power and gain are 43.7 dBm and 9.7 dB, respectively, while the efficiency at 6 dB output power back-off is 59.2%. The designed D-DPA eliminates the efficiency pit of the traditional two-way DPA in the output power back-off region.

Highly Efficient and Linearity-Enhanced Quasi-Balanced Doherty Power Amplifier at 3.5 GHz: Linear Quasi-Balanced Doherty Power Amplifier Design Methodology

The prestigious High-Efficiency Power Amplifier (HEPA) Student Design Competition (SDC) has been held annually for 17 years. In 2021, the competition was held virtually, live streamed from Keysight Technology’s Microwave Measurements Lab on 15 October 2021. The contest, organized by the IEEE Microwave Theory and Technology Society in collaboration with Keysight Technology, provides an opportunity for students from around the world to compete in the design of power amplifiers (PAs) with high linearity and high efficiency over a specified instantaneous bandwidth.

Broadband Doherty Power Amplifier Using Short Ended λ/4 Transmission Lines Based on the Analysis of Negative Characteristic Impedance

This paper presents a broadband Doherty power amplifier (DPA) using quarter-wavelength ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> /4) transmission lines with negative characteristic impedance. In conventional DPA designs, the load modulation network is frequency-dependent, leading to bandwidth limitation at the back-off power region. In this design, by integrating two <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> /4 transmission lines with negative characteristic impedance into the main and auxiliary branches, the impedance at the back-off power can be manipulated to maintain high efficiency at back-off power over a wide frequency range. Thus, the operational bandwidth is extended. In circuit realization, the two negative characteristic impedance <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\lambda $ </tex-math></inline-formula> /4 transmission lines are replaced by paralleled negative LC components. Then, the negative capacitor is combined into the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pi $ </tex-math></inline-formula> -shaped impedance matching network, while the negative inductor is eliminated by introducing Norton transformation. For verification, a broadband DPA with a fractional bandwidth of 108.6% from 0.8 to 2.7 GHz is implemented. The measured saturated output power is 41.8-44 dBm. The saturated and 6-dB back-off power drain efficiencies are 47.6%-84.4% and 39.5%- 52%, respectively. A 20-MHz LTE modulated signal with peak-to- average power ratio (PAPR) of 7.5 dB is also applied to measure the fabricated DPA. After digital predistortion, the adjacent channel leakage ratio (ACLR) better than −45.35 dBc is achieved, and the measured average efficiency is higher than 40% within the operating band.

Application of X‐parameter model of gallium nitride device for a continuous broadband Doherty power amplifier design

AbstractThe design of a continuous broadband Doherty power amplifier (DPA) based on an X‐parameter model is presented in this work. The broadband load‐pull X‐parameter model is extracted at both the package plane and current generate plane of the device under test. The model cannot only predict the fundamental and harmonic nonlinear behavioral accurately, but also find the optimal output power and drain efficiency (DE) region of the Smith chart precisely, thereby assisting DPA design. A 10‐W gallium nitride packaged transistor from Wolfspeed is utilized in this design. The fabricated DPA reached a saturation output power of 44.3 dBm, with a saturation DE over 68% and a 6 dB output power back‐off efficiency over 51% in the frequency range of 1.1–1.8 GHz, verifying experimentally the effectiveness of the proposed design methodology.

A Novel Approach for Doherty PA Design Using a Compact L-C Combiner

In this brief, a new combiner analysis method for the design of Doherty Power Amplifiers (DPA) is proposed. A compact L-C combiner is used to validate the proposed method through both simulation and realization of a two-stage DPA in a 130nm RF-SOI process. Using a 2.3GHz CW signal, the PA achieves a measured peak PAE of 51% at 32dBm output power under 3.4V supply voltage. From 2.1GHz to 2.5GHz, the PA shows an average output power and PAE higher than 26.9dBm and 39% respectively at −35dBc E-UTRA ACLR when using a 10MHz-50RB QPSK LTE uplink signal with memoryless DPD. At 2.3GHz, the PA achieves a linear Pout and PAE of 28.85dBm and 42.8% respectively.

Miniaturized Broadband Doherty Power Amplifier Using Simplified Output Matching Topology

This paper presents a Doherty power amplifier (DPA) with reduced size and wide bandwidth by using a simplified output matching topology. In broadband DPA designs, post-matching networks are usually added after the combing node, which usually occupy large circuit sizes. However, in this design, the post-matching network is not used. Instead, two ideal transformers and specific output matching components are employed at carrier and peaking branches. Then, by rearranging the output matching components in the two branches, Norton transformation can be used and the ideal transformers can be eliminated. In this way, the impedance at the combining node is directly matched to a 50- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> load without using a post-matching network, resulting in both compact size and wide bandwidth. For verification, a broadband DPA prototype with a very simple structure is implemented. The fabricated circuit shows a compact size. A wide bandwidth from 1.3 to 2.8 GHz (73%) is achieved with a saturated output power of 41.4–44.6 dBm. The drain efficiencies at saturation and 6-dB back-off power level are 60.1–79.1% and 41.8–61%, respectively, which are comparable to those of state-of-the-art designs.

A novel compact asymmetric Doherty PA design using symmetric transistors

AbstractA novel 7.2 dB output power back off Doherty power amplifier (DPA) based on asymmetrical load is proposed using two same transistors in this paper. To get maximum efficiency at back‐off output power and the largest saturate output power level simultaneously, the carrier power amplifier (PA) is matched to the maximum efficiency region when peaking PA is almost off, and both of the two PAs are matched to maximum power region to get largest output power. According to the proposed design methodology, high efficiency at back‐off power and high peak power DPA is designed and fabricated with two Cree's GaN HEMT CGH40010F devices. Measurements results show that the saturated output power of the DPA is over 44.5 dBm, the drain efficiency when 7.2 dB output power back off and saturate power are above 42% and 53%, respectively, in the range of 3.4–3.8 GHz. Meanwhile, better than −47.8 dBc adjacent channel leak power ratio can be achieved with digital predistortion under 20 MHz LTE signal testing at 3.4 GHz, the final design size is only 14 × 12 cm2.

A Broadband Asymmetric Doherty Power Amplifier Design Based on Multiobjective Bayesian Optimization: Theoretical and Experimental Validation

In this paper, a new multi-objective Bayesian optimization (BO) algorithm is applied to design a broadband gallium nitride (GaN) based Doherty power amplifier (DPA). The optimization process can be automatically implemented by combing the proposed methodology with a commercial simulation software. The performance of the DPA optimized by the proposed method is compared with those obtained with the initial designed DPA, the DPA optimized by existing BO method, and DPA optimized by the optimizers built-in using the commercial software advanced design system (ADS). The comparison results reveal that the DPA designed with the proposed method can achieve better performance with less optimization time than other optimization methods. The measured results show that the optimized DPA with the proposed method achieves a 9-dB back-off efficiency of 44.6%-65% and a saturated efficiency of 60.5%-78% from 2.0 GHz to 2.6 GHz, with saturated output power varying from 43.8 dBm to 45.2 dBm.

A planner Doherty power amplifier with harmonic suppression with open and short ended stubs

Abstract This paper presents a new Doherty power amplifier (DPA) with harmonics suppression. A Wilkinson power divider (WPD) with open-ended and short-ended stubs is designed to suppress unwanted signals. To design the power divider in the circuit of the DPA, even and odd mode analyses are utilized. The proposed design operates at range of 1.2–1.6 GHz. The linearity of the suggested DPA is increased about 6 dBm, in comparison with the main amplifier. The designed Doherty amplifier has a power added efficiency (PAE), drain efficiency (DE) and Gain about 60, 61% and 19 dB, respectively. The designed WPD suppresses 2nd up to 14th harmonics with more than 20 dB suppression level, which is useful for suppressing unwanted harmonics in DPA design. ATF-34143 transistors (pHEMT technology) are used for this DPA amplifier design. The main amplifier has class-F topology and class-F inverse topology is used for auxiliary amplifier.

Peak-Current-Ratio-Enhanced Compact Symmetrical Doherty Amplifier Design by Using Active Harmonic Control

This article proposes a new and compact symmetrical Doherty power amplifier (DPA) configuration that provides extended output-back-off (OBO) and enhanced load modulation. The concept of active harmonic control (AHC) is introduced to remedy the reduced-conduction-angle operation of the class-C auxiliary device, providing enhanced auxiliary current and power capability. Semianalytical study based on generalized load-modulation theory and large-signal simulation reveal that an optimal AHC can offer increased peak current ratio, improved load modulation, boosted output power, and power utilization factor (PUF). Besides, a new output combiner, with the inclusion of parasitic effect, is devised for ultracompactness and simplicity. For verification, a 11-dB-OBO 2-GHz symmetrical DPA based on GaN HEMT transistors is designed, fabricated, and measured. Excellent performance with drain efficiency of 74% (52%) is obtained at saturation (back-off of 11 dB). Moreover, a saturation power of 42.98 dBm is achieved, corresponding to an uplifted PUF of 1.25 (compared with conventional symmetrical DPA design). Under 20-MHz modulated signal (peak-to-average power ratio of 11 dB) excitation, the prototype exhibits average efficiency of 53.2% at an average output power of 32 dBm. The adjacent channel leakage power ratio (ACLR) is found to be −27.5 and −50.9 dBc before and after digital predistortion, respectively.

Modified load‐modulation network with two π ‐type high‐pass equivalent λ/4 lines for wideband compact GaN MMIC Doherty power amplifier design

Modified load‐modulation network with two <i>π</i> ‐type high‐pass equivalent λ/4 lines for wideband compact GaN MMIC Doherty power amplifier design

Symmetrical Doherty power amplifier design via continuous harmonic-tuned Class-J mode

This paper proposes bandwidth and efficiency improvements of symmetrical Doherty power amplifiers (SDPAs) using continuous harmonic-tuned Class-J mode (CHTCJM). By this approach, the effects of the CHTCJM on the impedance inverter network and post-matching network in SDPAs are reanalysed using formulated mathematical equations. In this way, to recover and further improve the bandwidth and efficiency performances in the conventional SDPA. The term recovery as proposed in this context is to redefine, reanalyse, retrieve and further enhance the output-power-back-off efficiency and bandwidth performances lost in the conventional SDPAs using an alternative theoretical methodology based on the CHTCJM. Based on the findings, the proposed technique can substantially recover and enhance the bandwidth and efficiency of SDPAs at the desired output-power-back-off level. According to the measurement results, the fabricated SDPA model operates within 1.45–2.45 GHz frequency band with more than 50% peak drain efficiency at 6 dB output-power-back-off. Furthermore, more than 60% drain efficiency, 12 dB gain and 43 dBm output power are delivered at saturation. Using digital predistortion with a 20-MHz long-term evolution signal in testing the linearity of the implemented SDPA, the SDPA’s adjacent channel leakage ratio is less than −45 dBc at an average output power of 36 dBm.

A broadband Doherty power amplifier design by optimizing its load modulation network

A broadband Doherty power amplifier design by optimizing its load modulation network