Digital Logic Design Research Articles

The Practical Reform in Basic Courses under the Educational Philosophy of CDIO-the Course of “Digital Circuits and Logic Design” as an Example

In order to promote the curriculum reform of our university and further expand the digital informatization in higher education, this paper targets several teaching reforming issues in the electronic information discipline of our university. Guided by the CDIO-OBE teaching philosophy, multifaceted teaching strategies are proposed for the major, such as overall planning of talent cultivation, teaching methods of teachers, and advanced evaluations of core basic courses. Starting from the compulsory course of 'Digital Circuits and Logic Design', the top-down implementation of practical reforms and the effects of updating teaching team, and continuously improvement on setting experiments are analyzed. Based on the feedback from students’ survey, it is confirmed as well that only through the effective integrations of digital technology and the higher-level blended teaching methods, and continuously optimized experiment reforms together can fundamentally promote the discipline construction and talent cultivation in the major of electronic information. Furthermore, through the closed-loop feedback of quantitative data from students’ questionnaires, the practical reforms facilitate the digitization transformation of basic courses in our university.

Implementation of 4-bit Universal Shift Register using Reversible Logic

The field of digital logic design is increasingly exploring reversible logic due to its potential in minimizing power dissipation, an essential criterion in low-power applications. This paper presents the design and implementation of a 4-bit universal shift register (USR) using reversible logic gates. The design leverages Fredkin gates, multiplexer (MUX), and D flip-flops to achieve functionality with minimal power consumption. Simulation results demonstrate the efficiency and effectiveness of the proposed design. Reversible logic is essential to low-power digital design and quantum computing because it makes it possible to reconstruct input signals from output signals, which reduces heat generation and information loss. The suggested shift register can be used for hold, parallel load, and left and right shift operations. To implement the functions of the shift register, we used a variety of reversible gates, including the Toffoli and Fredkin gates. When the architecture is contrasted with traditional non-reversible shift registers, it shows notable gains in reduced gate count and power efficiency

New Type of Extended Soft Set Operation: Complementary Extended Union Operation

Soft set theory was proposed by Molodtsov in 1999 to model some problems involving uncertainty. It has a wide range of theoretical and practical applications. Soft set operations constitute the basic building blocks of soft set theory. Many kinds of soft set operations have been described and applied in various ways since the inception of the theory. In this paper, to contribute to the theory, a new soft set operation, called complementary extended union operation, is defined, its properties are discussed in detail to obtain the relationship of each operation with other soft set operations, and the distributions of these operations over other soft set operations are examined. We obtain that the complementary extended union operation along with other certain types of soft set operations construct some well-known algebraic structure such as Boolean Algebra, De Morgan Algebra, semiring, and hemiring in the set of soft sets with a fixed parameter set. Since Boolean Algebra is fundamental in digital logic design, computer science, information retrieval, set theory and probability; De Morgan Algebra in logic and set theory, computer science, artificial intelligence, circuit design; semirings in theoretical computer science, optimization problems, economics, cryptography and coding theory, and hemirings in combinatorics, mathematical economics, theoretical computer science, these algebraic structures provide essential tools for various applications, facilitating the analysis, design, and optimization of systems across many disciplines, and thus this study is expected to contribute to decision-making methods and cryptography based on soft sets.

Research on the design and model of ideological and political teaching of the “Digital Circuit and Logic Design” course

Since the Ministry of Education put forward the requirements of promoting the ideological and political construction of college courses, colleges, and universities have actively designed and explored various professional courses’ ideological and political teaching construction. Taking “Digital Circuit and Logic Design” as an example, this paper constructs the teaching design, teaching model reforms, and the evaluation method of the practical approach by analysing the course’s characteristics, objectives, and current situation. It discusses the implementation path of promoting the ideological and political education of the “Digital Circuit and Logic Design” course.

FPGA-Based Implementation of SCADA System for Fuel Management

With the emergence of Digital Processors and Logic Design technologies, like FPGAs, the trend of using IC-based plug-and-play modules has been minimized. The focus is commercial off-shelf designing and developing modules and sub-modules on new FPGA technology. Some of the critical factors that make FPGA more suitable include enormous computational power, capabilities to perform logic operations, high-speed clocks, fast memory, and various built-in primitives for computation-intensive arithmetic operations. FPGA becomes suitable for implementing data capturing and processing systems with these characteristics. This paper is about designing and developing an FPGA-based Supervisory Control and Data Acquisition (SCADA) System to monitor and control the fuel level transition between two tanks that generally are designed using PLC. PLC-based SCADA systems are easy to implement, but when discussing performance, PLC cannot replace FPGA. The FPGA chosen is Spartan-3 due to its low cost and meeting the industrial temperature needs. At the same time, it may be translated into any advanced FPGA, producing fewer sources and power consumption benefits. The simulator is Xilinx 14.7 ISE, along with SDK. The implemented system provides the inherent amenities of SCADA along with the benefits of high speed, more accuracy, reduced and predictable delay, and a purely digitized system facilitated by the FPGA.

Design of QCA based N-bit single layer shift register using efficient JK Flip Flop for nano-communication applications

Quantum-dot Cellular Automata (QCA) is a technology that has the potential to create nano communication systems that are both highly efficient in power consumption and compact in size When compared to CMOS enabled electronic devices, QCA can achieve faster operation speed, higher density and lower power dissipation which becomes a boon, in digital logic design. In this paper, proposed work of designing sequential circuits using QCA has been achieved. An efficient JK flip-flop design along with 2-bit, 3-bit, 4-bit and 8-bit shift registers which can be further scaled up to N-bits using the same proposed design of flip-flop is observed. Also, the fault tolerance of proposed JK flip-flop design against single cell addition and deletion defects are presented in this paper. After conducting a performance comparison and thorough analysis of energy dissipation, it has been determined that the proposed designs bear lower cost and lower energy dissipations. Using QCADesigner tool, the validation of functions and processes of all proposed sequential designs has been done accordingly.

Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis

In very large-scale integration (VLSI) circuits, a partial of energy lost leads to information loss in irreversible computing because, in conventional combinatorial circuits, each bit of information generates heat and power consumption, thus resulting in energy dissipation. When information is lost in conventional circuits, it will not be recoverable, as a result, the circuits are provided based on the reversible logic and according to reversible gates for data retrieval. Since comparators are one of the basic building blocks in digital logic design, in which they compare two numbers, the aim of this research is to design a 1-bit comparator building block based on reversible logic and implement it in the QCA with the minimum cell consumption, less occupied area, and lower latency, as well as to design it in a single layer. The proposed 1-bit reversible comparator is denser, cost-effective, and more efficient in quantum cost, power dissipation, and the main QCA parameters than that of previous works.

Notice of Violation of IEEE Publication Principles: A Better Approach to Teaching Digital Logic Design to Engineering Undergraduates Than Using Only One of MSI/SSI, Schematic Entry or HDLs

Notice of Violation of IEEE Publication Principles A Better Approach to Teaching Logic Design to Engineering Undergraduates than Using Only One of MSI/SSI, Schematic Entry or HDLs By M.L. George, L. Ngalamou, in the IEEE Transactions on Education, Early Access After careful and considered review of the content and authorship of this paper by a duly constituted expert committee, this paper has been found to be in violation of IEEE's Publication Principles. This paper contains substantial duplication of original text from the papers cited below. The original text was copied without attribution (including appropriate references to the original author(s) and/or paper titles) and without permission. Due to the nature of this violation, reasonable effort should be made to remove all past references to this paper, and future references should be made to the following articles: Enhancing Learning Effectiveness in Design Courses Through the Use of Programmable Logic Boards, by Yi Zhu, T. Weng, Chung-Kuan Cheng, in the IEEE Transactions on Education, Vol.52, No.1, February 2009, pp.151-156 Digital design and programmable logic boards: Do students actually learn more? by T. Weng, Yi Zhu, Chung-Kuan Cheng, in the Proceedings of the 38th Annual Frontiers in Education Conference, 2008. FIE 2008, October 2008 This paper explores the teaching of digital logic design to engineering undergraduates at the University of the West Indies (UWI), St. Augustine , Trinidad and Tobago, using the three methods MSI/SSI, schematic entry, and hardware description using VHDL. This paper serves to compare the performance of students when each of these three methods is used. In conclusion, this paper proposes a better approach to teaching digital logic design to engineering undergraduates than that of using only one of the three teaching methods explored.

TCAD analysis of tunnel field effect transistor using Ge material for low power application

Low power is important parameter for any semiconductor devices. In transistors the current flow between source to drain through channel region is dependent upon the materials of source, drain and channel. This paper presents a detailed study of the role of Technology Computer-Aided Design (TCAD) simulations of tunnel-field-effect-transistor (TFET) for low power applications with Germanium (Ge) material. Ge has band gap 0.66 V and the most suitable candidate to improve TFET performance. The need and importance of TCAD tool in semiconductor technology development is explained in details in this manuscript. It also elaborates the TCAD techniques for designing a device, parameter extraction and different models that are used to design different TFET structure. TCAD based digital logic design, design for manufacturing, memory designing and reliability study have been also discussed in this paper.

CMOS Implementation of 5T SRAM with Low Power Dissipation

SRAM is a very fast memory with low power consumption. The main objective of this work is to perform a 64-digit SRAM with 90 nm innovation. Execution depended on a granular perspective. SRAM's base module is similar to an N-MOS inverter, flip-flop, and semiconductor. We design this module according to the configuration rule of the ? format. Using Harvard technology, SRAM can easily retrieve information from memory. To create advanced rational circuits, it is important to see how an SRAM is assembled and how it works. The bottom line is that with 0.12 micron 90nm technology, we are developing a 5T SRAM and we can read and write. It is a fundamental part of a computer's central processing unit. RAM is a building block made up of several circuits. The 64-bit SRAM reader was developed with MICROWIND and DSCH2. With the MICROWIND program, the developer can design and simulate an integrated circuit at the physical description level. DSCH2 allows switching of digital logic design.

CoCEC: An Automatic Combinational Circuit Equivalence Checker Based on the Interactive Theorem Prover

Checking the equivalence of two Boolean functions, or combinational circuits modeled as Boolean functions, is often desired when reliable and correct hardware components are required. The most common approaches to equivalence checking are based on simulation and model checking, which are constrained due to the popular memory and state explosion problems. Furthermore, such tools are often not user-friendly, thereby making it tedious to check the equivalence of large formulas or circuits. An alternative is to use mathematical tools, called interactive theorem provers, to prove the equivalence of two circuits; however, this requires human effort and expertise to write multiple output functions and carry out interactive proof of their equivalence. In this paper, we (1) define two simple, one formal and the other informal, gate-level hardware description languages, (2) design and develop a formal automatic combinational circuit equivalence checker (CoCEC) tool, and (3) test and evaluate our tool. The tool CoCEC is based on human-assisted theorem prover Coq, yet it checks the equivalence of circuit descriptions purely automatically through a human-friendly user interface. It either returns a machine-readable proof (term) of circuits’ equivalence or a counterexample of their inequality. The interface enables users to enter or load two circuit descriptions written in an easy and natural style. It automatically proves, in few seconds, the equivalence of circuits with as many as 45 variables (3.5 × 10 13 states). CoCEC has a mathematical foundation, and it is reliable, quick, and easy to use. The tool is intended to be used by digital logic circuit designers, logicians, students, and faculty during the digital logic design course.

Characterizing a standard cell library for large scale design of memristive based signal processing

In recent years, the use of memristors in circuits design has rapidly increased and attracted research interest. Advances have been made to both the size and the complexity of memristor designs. Therefore, computer aided design tools are required to handle memristor-based large-scale designs. A comprehensive automatic framework for the design and synthesis of large-scale memristor-complementary metal-oxide-semiconductor (CMOS) circuits is described herein. This framework provides a synthesis approach that can be applied to all memristor-based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor-based logic cells to generate a standard cell library file for large-scale simulation. The proposed architecture is based on RRAM and ReRAM redox-based devices and the memristor ratioed logic design approach. The proposed framework is implemented in the Cadence Virtuoso schematic-level environment and was verified with Verilog-XL, MATLAB, and the electronic design automation synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. Nevertheless, it is perfectly suitable for signal processing applications that require MATLAB functions to produce text files with hex values in order to overcome the limitations of the simulation environment. A framework is deployed herein for design of the memristor-based parallel 8-bit adder/subtractor and a 2D memristive-based median filter. Both proposed designs memristor-based adder/subtractor and memristive median filter have significant power reductions of 66% and 16% respectively, when compared to the same designs using CMOS technology.

Why Are Hardware Description Languages Important for Hardware Design Courses?

Curricula in computer engineering, computer science, and other related fields include several courses about hardware design. Examples of these courses are digital logic design, computer architecture, microprocessors, computer interfacing, hardware design, embedded systems, switching theorem, and others. In order for the students to realize the concepts taught in such courses, practical track should be reinforced along with the theoretical track. Many universities offer to their students labs in which they can practice hardware design. However, students need more than that: they need tools that enable them to design, model, simulate, synthesize, and implement hardware designs. Although high-level programming languages like Java and C++ could be an option, it might be a tedious task to use them for this mission. Fortunately, hardware-description languages (HDLs) have been specifically devised for this purpose. This paper shows some of the great features of HDLs and compare using them with using C++ for illustrating digital concepts through salient examples.

Extended Boolean algebra for asynchronous quasi‐delay‐insensitive logic

Asynchronous quasi-delay-insensitive (QDI) circuits have recently become an active research area in digital logic design. In contrast with synchronous paradigms, QDI approaches utilise threshold gates with hysteresis, such as Muller C-element and null convention logic (NCL) gates. However, there are no existing methods to explicitly describe these hysteretic logic gates in Boolean algebra. Therefore, in this study, the authors extend the Boolean algebra with two novel operators, named completion and truth tuple, to enable explicit expressions for all QDI elements such as C-elements, NCL, NCL+, latches and several non-conventional hysteretic threshold gates that they call dual-threshold logic. In addition, they develop a set of 16 laws and theorems for these new operators to create a complete novel algebraic extension for QDI logic. It is demonstrated that the authors' extended algebra is a complete approach for explicit design and analysis of QDI circuits, including logic description, equation formation from truth table, expression simplification and conversion, and even gate mapping and corresponding CMOS implementation. They also provide an analysis and solution for netlist corruption problems during the synthesis process of existing QDI design flows, as well as a complete design example using the extended Boolean algebra with different QDI design styles.

A tool for facilitating the automated assessment of engineering/science courses

In recent years, massive open online courses (MOOCs) have become quite popular. Such courses are either completely free or cost nominally. Generally, the MOOCs face the challenge of not being recognized as ‘regular’ courses (i.e., the ones taken at the traditional learning institutions). One of the main reasons for this lack of acceptability is the assessment in an unsupervised environment, which is prone to the problems of test-taker’s online lookups or interaction with others for finding the answers to the test questions. A few ways of alleviating this problem include: limiting the time for answering the questions, the avoidance of repetitive questions, and the creation of a large number of questions. This paper presents a tool named QAgen that enables the automatic creation of a large number of questions and answers related to different topics in computer/electrical engineering (ECE), computer science, physics, etc. Specifically, the tool is related to the courses on digital logic design, computer architecture, etc. The generated questions are in a format that is suitable both for learning management system (LMS) based and/or non-LMS-based assessment in conventional courses or MOOCs. The proposed tool is based on open-source software, thus eliminating the need for any commercial software packages. The underlying principles of QAgen are applicable to other engineering/science courses as well, if the assessment methods require the creation of some connected-object diagrams, tables and equations. For assessing the usefulness of QAgen, practice question sets were created for three different courses. The student surveys for these courses indicated that the questions helped students prepare for actual tests/examinations. Especially favored by the students was the availability of correct answers at the end of each practice test/examination.

Design of ternary logic gates and circuits using GNRFETs

In this study, the design of digital logic gates and circuits in ternary logic is presented. The ternary logic is observed to be a better alternative to the traditional binary logic because it offers faster computations, smaller chip area, and lesser interconnects. Thus, it allows designing the low-complex, high-speed, and energy-efficient circuits in future digital design. A novel technique is proposed to design the ternary logic gates using multi-threshold graphene nanoribbon field-effect transistors (GNRFETs). The GNRFET threshold voltage is controlled by the width of the graphene nanoribbon, which is defined by the dimer lines number. Three different inverters are designed namely standard, positive, and negative inverters along with the basic and universal logic gates. Additionally, the ternary half adder and full adder are proposed that further helps to design the complex arithmetic circuits. All the proposed ternary logic circuits have been extensively simulated in SPICE for functional verification and performance analysis. The performance of the proposed ternary logic circuits is compared with the existing designs presented in the literature. The comparison results show that the propagation delay and circuit area of GNRFET-based circuits are reduced with an average of 41.3 and 64%, respectively, than the existing ternary circuits.

Electronics-Free Logic Circuits for Localized Feedback Control of Multi-Actuator Soft Robots

The vision of creating entirely-soft robots capable of performing complex tasks will be accomplished only when the controllers required for autonomous operation can be fully implemented using soft components. Despite recent advances in compliant fluidic circuitry for mechanical signal processing, the applicability of this technology for soft robot control has been limited by complicated fabrication and tuning processes, and also the need for external signals such as clocks and digital references. We propose a method to develop pneumatic soft robots in which coordinated interactions between multiple actuators are performed using controllers implemented on components distributively embedded in the soft structures of the system. In this approach, the notions of binary and multi-valued actuator logic states are introduced. In this way, the physical local dynamical couplings between the analog states of the actuators, established using soft valves of a new type, can be thought of as logic-gate-based mappings acting on discretized representations of the actuator states. Consequently, techniques for digital logic design can be applied to derive the architectures of the localized mechanical couplings that intelligently coordinate the oscillation patterns of the actuator responses. For the purposes of controller tuning, the soft valves are conceived so that their main physical parameters can be adjusted from the exterior of the robot through simple geometrical changes of the corresponding structural elements. To demonstrate the proposed approach, we present the development of a six-state locomoting soft robot.

Verilog HDL and its ancestors and descendants

This paper describes the history of the Verilog hardware description language (HDL), including its influential predecessors and successors. Since its creation in 1984 and first sale in 1985, Verilog has completely revolutionized the design of hardware. Verilog enabled the development and wide acceptance of logic synthesis. For large-scale digital logic design, previous schematic-based techniques have transformed into textual register-transfer level (RTL) descriptions written in Verilog. As of 2018 about 80% of integrated circuit design teams worldwide use Verilog and its compatible descendant SystemVerilog.

Lecture-Free Classroom: Fully Active Learning on Moodle

Contribution: This article shows that today’s learning technologies have the potential to make lectures unnecessary by supporting student’s active learning in the classroom. Background: Despite worries about their pedagogical effectiveness, lectures remain the main instructional method in university classrooms. Introducing active learning into the classroom can be difficult due to class sizes and the challenge of providing appropriate scaffolding to individual students. This article shows that a thoughtful deployment of today’s learning technology can help in structuring a whole course as a set of activities, which can improve students’ engagement in the classroom. Intended Outcomes: With this full engagement in the classroom, students’ affective and learning attitudes as well as their learning performance are expected to improve. Application Design: Moodle was used to design learning activities for second-year students taking a digital logic design course in an electrical and computer engineering program. Throughout the semester, the students used the class time entirely to complete these activities and reflect on them. The instructor’s role in the classroom was limited to interaction with individual students or teams to clarify any questions. He did not give any lectures during the term. Findings: A total of 103 students took this course in Fall 2018 and Spring 2019. The students showed a strong acceptance of the presented instructional design. Their evaluation of individual learning activities was consistently positive and their performance in the final exam has improved considerably compared to the previous offerings of the course.

A low-cost dual-axis solar tracking system based on digital logic design: Design and implementation

Nowadays, photovoltaic (PV) systems have been being installed rapidly all over the world. However, the installations typically employ a fixed flat-plate system, using pre-specified angles acquired by geographical positioning. Hence, the power generated by PV systems decreases significantly, according to the variation of solar irradiation in the progress of a day and the seasons in a year. In order to increase the solar power generation, this paper proposes the design and implementation of a low-cost automatic dual-axis solar tracker system. The tracking system is designed as a closed-loop control based active tracking system, employing Light Dependent Resistor (LDR) sensors as the inputs of the system. The tracking strategy utilizes a digital logic design of the sensors’ participation implemented in a pseudo-azimuthal system to simply rotate around the primary (north-south) axis and the secondary (east-west) axis. In the experiment, the proposed tracking system and the fixed flat-plate system were evaluated for the comparative study. The experimental results show that the proposed tracking system increased the efficiency of electrical energy by averagely 44.89%, using the proposed system compared with the fixed flat-plate system. Finally, the cost analysis is provided for the proposed tracking system.