CMOS Implementation of 5T SRAM with Low Power Dissipation

Abstract

SRAM is a very fast memory with low power consumption. The main objective of this work is to perform a 64-digit SRAM with 90 nm innovation. Execution depended on a granular perspective. SRAM's base module is similar to an N-MOS inverter, flip-flop, and semiconductor. We design this module according to the configuration rule of the ? format. Using Harvard technology, SRAM can easily retrieve information from memory. To create advanced rational circuits, it is important to see how an SRAM is assembled and how it works. The bottom line is that with 0.12 micron 90nm technology, we are developing a 5T SRAM and we can read and write. It is a fundamental part of a computer's central processing unit. RAM is a building block made up of several circuits. The 64-bit SRAM reader was developed with MICROWIND and DSCH2. With the MICROWIND program, the developer can design and simulate an integrated circuit at the physical description level. DSCH2 allows switching of digital logic design.