Design Of Counter Research Articles

Optimized Design of a Converter Decimal to BCD Encoder and a Reversible 4-bit Controlled Up/Down Synchronous Counter

The field of quantum computing, reversible logic, and nanotechnology have earned much attention from researchers in recent years due to their low power dissipation. Quantum computing has been a guiding light for nanotechnology, optical computing of information, low power CMOS design, computer science. Moreover, the dissipation of energy in the field combina-torial logic circuits becomes one of the most important aspects to be avoided. This problem is remedied by a reversible logic favoring the reproduction of inputs to outputs, which is due to the absence of unused bits. Every bit of information not used generates a loss of information causing a loss of energy under the form of heat, the reversible logic leads to zero heat dissipation. Among the components affected by reversible logic are binary reversible counter and converter from decimal to BCD encoder(D2BE) which are considered essential elements. This article will propose an optimized reversible design of a converter from decimal to BCD encoder (D2BE) and an optimized design of reversible Binary counter with up/ down. Our designs show an improvement compared to previous works by replacing some reversible gates with others while keeping the same functionality and improving performance criteria in terms of the number of gates, garbage outputs, constant inputs, quantum cost, delay, and Hardware complexity.

Improvements to the long counter for neutron energies up to GeV

An improved design of neutron long counter has been developed. Twelve chromium rods were implemented into the moderator, which extended the response to the GeV region. The dimensions and geometry were varied and the consequences on the response function were studied. Different parameters were optimized based on Monte Carlo code to flatten the neutron response energy distribution, over a wide energy range, from a few eV’s to 1 GeV without significant changes in the response observed, and a deviation less than 15.5% in the range of 1 eV to 800 MeV can be obtained.

Optimized Counter Design for Accelerated Summation in Digital Signal Processing Systems

Efficient summation of multiple operands in parallel is crucial in various digital signal processing units. Accelerating this summation process requires high compression ratio counters and compressors. This study introduces a novel approach to fast saturated binary counters and exact/approximate (4:2) compressors utilizing sorting networks. The counter's inputs are asymmetrically divided into two groups and processed through sorting networks to produce reordered sequences, efficiently represented by one-hot code sequences. By establishing three special Boolean equations between the reordered sequence and the one-hot code sequence, the output boolean expressions of the counter are significantly simplified. Simulation results demonstrate the superiority of the proposed method over conventional approaches in terms of performance.

Design and optimization of a proportional counter for the absolute determination of low-energy x-ray emission rates.

We recently presented the construction of a proportional counter for the absolute measurement of low-energy x-ray emission rates. Its main features were presented in a previous study, along with the testing of its performance as an absolute technique. Full details on its design, construction, and characterization processes are given in this paper. First, the analytical calculations and Monte Carlo simulations that led to the choice of optimal dimensions will be presented, followed by the study of the charge creation and the modeling of the electric field that confirmed that the criteria for a reproducible charge multiplication are met. Afterward, details on the electronics and gas control system will be provided. The dimensional measurements for the accurate determination of the solid angle will be described in detail. Special emphasis will be placed on the production of the detector window, which was made of reduced graphene oxide instead of beryllium. Some tests on the operation of the counter will be presented, namely, the measurement of spectra of several radionuclides that emit x-rays between 3 keV and 9 keV, as well as the fluorescence spectrum of chlorine, at 2.6 keV. A brief explanation of the determination of emission rates will be given, including the approach adopted for the treatment of the escape-peak area. The emission rate measured with the proportional counter was converted into activity concentration using the emission probabilities from the bibliography, in order to compare the results with those obtained by liquid scintillation counting, and both results were found to be in good agreement.

Design and test of bullet shell counter

In order to solve the problem of counting when the bullet shells is recovered, two different types of bullet shells counters are designed. Through theoretical analysis, the size of the slot in the slot type bullet shell counter is determined, and the best times of abrupt reverse of the slide mechanism in the chute type shell counter is determined through experiments. The comparison test of two kinds of bullet shell counter shows that: The ejection efficiency of the chute type bullet shell counter is 317.5 pieces / minute, and the counting accuracy is 99.00%; the counting efficiency of the slot type bullet shell counter is 113.2 pieces / minute, and the counting accuracy is 99.75%.The chute type bullet shell counter is suitable for high-efficiency counting when large-scale bullet shell is recycled, and the slot type bullet shell counter is suitable for small-scale accurate counting. Both kinds of bullet shell counters meet the requirements of automatic shell counting put forward by the army.

Overcoming the sensitivity vs. throughput tradeoff in Coulter counters: A novel side counter design

Microfabricated Coulter counters are attractive for point of care (POC) applications since they are label free and compact. However, these approaches inherently suffer from a trade off between sample throughput and sensitivity. The counter measures a change in impedance due to displaced fluid volume by passing cells, and thus the counter's signal increases with the fraction of the sensing volume displaced. Reducing the size of the sensing region requires reductions in volumetric throughput in the absence of increased hydraulic pressure and sensor bandwidth. The risk of mechanical clog formation, rendering the counter inoperable, increases markedly with reductions in the size of the constriction aperture. We present here a microfluidic coplanar Coulter counter device design that overcomes the problem of constriction clogging while capable of operating in microfluidic channels filled entirely with highly conductive sample. The device utilizes microfabricated planar electrodes projecting into one side of the microfluidic channel and is easily integrated with upstream electronic, hydrodynamic, or other focusing units to produce efficient counting which could allow for dramatically increased volumetric and sample throughput. The design lends itself to simple, cost effective POC applications.

Design of low power 16-bit counter with Programmable Combinational Logic and Integrated Clock Gating using 16-nm technology

ABSTRACT To demand high power back up by increasing the user’s need for applications in a single IC, the power dissipation takes place. The proposed two approaches are control Logic (CL) with Integrated Clock Gating (ICG) and Programmable Combinational Logic(PCL)and Gate Logic(GL) with ICG to achieve the low power and low dynamic leakage in 16-bit Counter. These approaches operate in different Logic to Generate/stop the clock for low-power digital circuits. The First approach of control Logic with ICG stops the clock only for single Most Significant Flip Flop Transistor. This approach consumes 1.6 mW and 15% more power savings than Existing. But the second approach only consumes 0.0261 mW power, which is 98% more power savings than a first proposed approach of CL with ICG and conventional counters. These dramatic boom power savings by stopping the clock for all redundant transition in Most Significant Flip Flop Transistors using PCL & GL with ICG. Analyse the second approach without ICG for 16-bit counter will consume 0.0334 mW, which consumes 21.96% high power than the presence of ICG in counter circuits. Moreover, the same proposed technique of the second approach applies for ISCAS’89 S444 circuits, which saves >90% power improvement than the conventional method and ordinary 16-bit counter-power analysis by the same technology, which consumes 42.42% high power than proposed low-power counter. The Low Power 16-bit counter design implementation using 16 nm Cadence Genustechnology, which attains the dynamic leakage with ICG is 0.170nW and without ICG is 0.177nW with an operating voltage of 0.8 V.

Divide-by-16/17 dual modulus prescaler design with enhanced speed in 180nm CMOS technology

In this work, we propose a high-speed dual modulus divide by 16/17 prescaler Design IV with 8.9 GHz operating rate. It uses RE-3 type DFF in synchronous divide by 2/3 prescaler design and asynchronous divide by 8 counter design. It reduces: design complexity, capacitive loading and delay. The proposed Design IV shows better results in terms of both speed and power performance than other ratioed and ratioless divide by 16/17 prescalers. It is implemented in a 180 nm CMOS technology and consumes only 0.38 mW power from a 1V supply voltage. The speed of the new Design IV is improved by ~53% compared with conventional circuits with operating frequency 5.8 GHz.

Smart Digital Bi-Directional Visitors Counter Based on IoT

This research presents the design of a smart digital bidirectional visitor counter (SDBVC). The million religious visits especially in Iraq increased the need for accurate smart counting systems for human to count the largest gathering of people in one place. The major focus is on counting huge number of humans enter one place from multiple entrance gates. The central processing unit (CPU) receives all the data from these gates and finally makes the studies about the overall human number, men number, women number, the period of the day that this number reach the highest and smallest number and etc. The proposed project hardware contains multiple Wi-Fi based Arduino microcontrollers (like Node-MCU Arduino): one Arduino in each gate which is called transmitter and one in CPU which is called receiver, multi ultrasonic sensors for each transmitter placed on the entrance gates (men gates data separated from women gates data). ThingSpeak.com is used to save the large recorded data for long time for example many days and give results and records about the number as Arba’een Pilgrimage for Imam Hussein shrine in Iraq. The proposed system gives accurate results on the number of entered and exit people to and from one place.

Simple design of memristive counters and their applications in automatic irrigation system

Memristor, a passive circuit element got tremendous research attention for its in-memory computation. In this study, it was identified that controllable resistive state transitions exist within a single memristor. On the basis of this realisation, a simple but unconventional implementation of memristive up and down counters was presented. Furthermore, a dual up-down counter was developed, which can mimic any real-time process variations. To demonstrate its practical application, a counter-based memristive automatic irrigation system was explicated, which provided optimised utilisation of electrical and water resources. The proposed study opens up a new purview in the area of future non-Von Neumann computer architectures and its potential electronic applications.

Design and Construction of the Digital Interruption Counter

Nowadays the electronic digital interruption counter is very popular. It counts and records automatically the number of objects passing on a conveyor belt or the people entering or leaving any place through a particular gate. The interruption of light beam in this circuit is counted in three digits up to 999. The digital interruption counter circuit is constructed by using locally available electronic components. The circuit is very simple and construct with TTL integrated circuits.

Design and Validation of a Holographic Particle Counter.

An in-line holographic particle counter concept is presented and validated where multiple micrometer sized particles are detected in a three dimensional sampling volume, all at once. The proposed Particle Imaging Unit is capable of detecting holograms of particles which sizes are in the lower m- range. The detection and counting principle is based on common image processing techniques using a customized Hough Transform with a result directly relating to the particle number concentration in the recorded sampling volume. The proposed counting unit is mounted ontop of a Condensation Nucleus Magnifier for comparison with a commercial TSI-3775 Condensation Particle Counter (CPC). The concept does not only allow for a precise in-situ determination of low particle number concentrations but also enables easy upscaling to higher particle densities (e.g., ) through its linear expandability and option of cascading. The impact of coincidence at higher particle densities is shown and two coincidence correction approaches are presented where, at last, its analogy to the coincidence correction methods used in state-of-the-art CPCs is identified.

Design and evaluation of a condensation particle counter with high performance for single-particle counting

A full-flow butanol-based condensation particle counter (CPC) with a concentration range from 0 to 2 × 105 particles/cm3 was developed to measure nanoparticles down to 4.5 nm. Good single-particle counting performance was achieved by developing a high-speed optical particle detection module. The pulse width of single particle was approximately 1.2 μs at a flow rate of 0.3 L/min. By establishing a heat and mass transfer model using the COMSOL simulation software, the effects of temperature and aerosol sampling flow on the condensation growth of nanoparticles were studied. The performance of developed condensation particle counter was evaluated through a series of experiments to determine the coincidence probability, concentration range, and detection efficiency (cutoff diameter). At concentrations of 1.5 × 104 particles/cm3 and 2 × 105 particles/cm3, the coincidence probabilities of the developed condensation particle counter were 9.5% and 55%, respectively. A 99.9% (R2) statistical correlation was obtained between the pulse-time corrected concentration of the developed condensation particle counter and the standard reference concentration. Finally, the experimental results showed that the developed condensation particle counter cutoff diameter, at which the detection efficiency was 50%, for sucrose aerosol particles was 4.5 nm.

An Optimized Counter Design using T Flip-Flop in Quantum-Dot Cellular Automata Technology

Conventional CMOS technology have lot of limitations and serious challenges threat this technology when scaled to a nano-level. Several alternative technologies have been proposed as solutions to overcome limitations and challenges encountered by CMOS. Quantum dot-cellular automata (QCA) is an emerging nanotechnology for the development of logic circuits such as combinational and sequential circuits.QCA seems to be best alternative to the conventional complementary metal-oxide semiconductor (CMOS) technology.QCA is a new computing paradigm in nanotechnology that can implement digital circuits with outstanding features such as ultralow power consumption, faster switching speed and extremely density structure . In this paper , a novel area efficient and optimized QCA layout design of sequential circuit T flip flop is proposed by which the QCA layout area has reduced by 57% , cell count improved by 56% in comparison with the earlier best designs. The use of proposed T flip flop in designing sequential circuits like synchronous 2 bit up counter,3 bit up counter and 4 bit up counter has reduced the QCA layout area by 65%,64% and 68% respectively where as QCA cell count are reduced by 53%, 62% and 59%.. The sequential circuits flip flop and counters are designed using three input XOR gate and are implemented by QCA layout. The paper also present the use of proposed T flip flop designed with 3 input XOR gate in designing not only synchronous binary up counters but also in synchronous binary down counter provides a significant reduction in the hardware and complexity than the existing methods. These circuits are simulated using computer aided design tool QCA Designer 2.0.3, which is a design and simulation tool for quantum dot cellular automata. The aim is to maximize the circuit density and focus on a QCA layout that uses minimal number of cells

Design and analysis of microfluidic cell counter using spice simulation

Microfluidic cytometers based on Coulter principle have recently shown a great potential for point of care biosensors for medical diagnostics. In this study, the design and characterization of Coulter-based microfluidic cytometer are investigated through electrical circuit simulations considering an equivalent electrical model for the biological cell. We explore the effects related to microelectrode dimensions, microfluidic detection volume, suspension medium, size/morphology of the target cells, and the impedance of the external readout circuit, on the output response of the sensor. We show that the effect of microelectrodes’ surface area and the dielectric properties of the suspension medium should be carefully considered when characterizing the output response of the sensor. In particular, the area of the microelectrodes can have a significant effect on cell’s electrical opacity (the ratio of cell impedance at high to low frequency) which is commonly used to distinguish between subpopulations of the target cells (e.g., lymphocytes vs. monocytes when counting white blood cells). Moreover, we highlight that the opacity response versus frequency can significantly vary based upon whether the absolute cell impedance or the differential output impedance is used in its calculation. These insights could provide valuable guidelines for the design and characterization of Coulter-based microfluidic sensors.

Musculoskeletal disorders, psychological distress, and work error of supermarket cashiers

AbstractBackgroundHuman physiological and psychological states may influence work performance. The aim of this study was to analyze the relationships among the musculoskeletal disorders (MSDs), psychological distress, and work error of supermarket cashiers. There were 443 Chinese supermarket cashiers surveyed in this study. Among these cashiers, 431 valid samples were obtained. The study surveyed the MSDs, psychological distress of supermarket cashiers with MSDs Likert scale and Symptom Checklist‐90 (SCL‐90) scale, respectively. The data of work error of each cashier was provided by the supermarkets managers. The increasing working years of Chinese supermarket cashiers were connected with increased MSDs. Significant differences were observed in MSDs and work error of cashiers from different supermarkets (different in checkout design). The physiological health and psychological distress of supermarket cashiers are important to work performance and require serious attention. Good checkout counter design with flat conveyor is helpful to reduce cashiers’ MSDs and work error.

Synchronous Counter Design Using Novel Level Sensitive T-FF in QCA Technology

The quantum-dot cellular automata (QCA) nano-technique has attracted computer scientists due to its noticeable features such as low power consumption and small size. Many papers have been published in the literature about the utilization of this technology for de-signing many QCA circuits and for presenting logic gates in an optimal structure. The T flip-flop, which is an essential part of digital designs, can be used to design synchronous and asynchronous counters. This paper presents a novel T flip-flop structure in an optimal form. The presented novel gate was used to design an N-bit binary synchronous counter. The QCADesigner software was used to verify the designed circuits and to present the simulation results, while the QCAPro tool was used for the power analysis. The proposed design required minimal power and showed good improvements over previous designs.

Study on cosmic test and QC method of high-rate MRPC for CBM-TOF

The CBM (Compressed Baryonic Matter) experiment constructed at FAIR (Facility for Anti-proton and Ion Research) at GSI, Darmstadt, Germany, will provide unique research opportunities to explore the phase diagram of nuclear matter. As one of the core detectors in the CBM experiment, the Time-of-Flight (TOF) system applies the MRPC (Multi-gap Resistive Plate Chamber) for a precise particle identification for all the incident charged hadrons. The CBM-TOF will be operated at an ion beam intensity up to 109/s, which means the particle fluxes on the TOF wall can reach an unprecedentedly high rate of 30 kHz/cm2. Almost half of the MRPC counters are from the inner region of the TOF wall, and they will be assembled with the low-resistive glass which enables them to work under such high rate. This is the first time of the large scale application of the low-resistive glass MRPCs into the nuclear and high-energy physics experiments. It is especially important to study on the production and test procedure to keep the good performance of all these counters. For this mass production, we have developed a set of specified manufacturing procedure and quality control method to guarantee the performance of all the counters. A newly developed method to check the uniformity of the gas gap with help of the projection imaging technique has been first applied. Until now, 73 MRPCs have been produced for the eTOF project in the BESII detector upgrade at STAR and the TOF system of mini-CBM. Tested by cosmic ray in a system based on TRB, all the produced counters show a stable performance of above 95% efficiency and below 90 ps time resolution. The study on the mass production of the low-resistive plate chamber will provide experience for wide application of MRPC into the high rate experiments in the future. In this paper, the counter design, manufacturing procedures, quality control methods and test results for this MRPC counter are described in a detailed way.

MULTI-CHANNEL FRY COUNTER DESIGN USING OPTOCOUPLER SENSOR

This paper describes a design of a fry counter intended to be used by consuming fish farmer. Along this time, almost all the fry counting process is counted by manual, which is done by a human. It is requiring much energy and needs high concentration; thus, can cause a high level of exhaustion for the fry counting worker. Besides that, the human capability and capacity of counting are limited to a low level. A fry counter design in this study utilizes a multi-channel optocoupler sensor to increase the counting capacity. The multi-channel fry counter counting system is developed as a solution to a limited capacity of available fry counter. This design uses an input signal extender system on controller including the interrupt system. From the experiment, high accuracy level is obtained on the counting and channel detection, therefore, this design can be implemented and could help farmers to increase the production capacity of consuming fish.

Design and Analysis of a Low Power Binary Counter-based Approximate Multiplier Architecture

Multiplication has become the fundamental arithmetic operation in modern electronic world. Many researches in Signal processing and image processing applications are looking for energy efficient architectures. These applications exhibit error tolerance thus laying foundation for approximation techniques. The proposed work utilizes a new binary counter for partial product accumulation in a segmentation based approximate multiplication technique. The fundamental building block of the counter is a 3-bit stack circuit, which combines each of “Logic 1” bits collectively, after which a stacking process is done to convert two 3-bit modules into a 6-bit stack module. The counter circuit is obtained by converting the bit stacks to binary counts, without any XOR gates on the critical line of operation. This leads to design of binary counters with effective yield of power and delay. Moreover, applying these counters for partial product accumulation in the approximate multipliers found to be more effective when compared with conventional techniques. In future, these counter based approximate multipliers can be utilized to design energy efficient filters for image processing and signal processing applications.