Optimized Design of a Converter Decimal to BCD Encoder and a Reversible 4-bit Controlled Up/Down Synchronous Counter

Sedra Moulay Brahim,Mariam El Ghazi,Issam Andaloussi

doi:10.14569/ijacsa.2021.01208103

Abstract

The field of quantum computing, reversible logic, and nanotechnology have earned much attention from researchers in recent years due to their low power dissipation. Quantum computing has been a guiding light for nanotechnology, optical computing of information, low power CMOS design, computer science. Moreover, the dissipation of energy in the field combina-torial logic circuits becomes one of the most important aspects to be avoided. This problem is remedied by a reversible logic favoring the reproduction of inputs to outputs, which is due to the absence of unused bits. Every bit of information not used generates a loss of information causing a loss of energy under the form of heat, the reversible logic leads to zero heat dissipation. Among the components affected by reversible logic are binary reversible counter and converter from decimal to BCD encoder(D2BE) which are considered essential elements. This article will propose an optimized reversible design of a converter from decimal to BCD encoder (D2BE) and an optimized design of reversible Binary counter with up/ down. Our designs show an improvement compared to previous works by replacing some reversible gates with others while keeping the same functionality and improving performance criteria in terms of the number of gates, garbage outputs, constant inputs, quantum cost, delay, and Hardware complexity.

Highlights

In the irreversible logic, the design of circuits becomes more and more difficult in terms of material design, this is due to the dissipation of energy in the form of heat which is generated at the end of the lost or unused bits
4) Quantum Cost (QC): The Quantum cost (QC) is calculated by counting the number of one input–output and two input–output reversible gates used in realizing a circuit [19,20]
3) Design4: In 2016 KUNAL CHAUDHARY [13] devised a design for the converter from decimal to BCD encoder is composed of four reversible gates Fredkin Gate FRG and three reversible gates FG in the following figure (Fig. 4)

Summary

INTRODUCTION

The design of circuits becomes more and more difficult in terms of material design, this is due to the dissipation of energy in the form of heat which is generated at the end of the lost or unused bits. Fredkin and Toffoli have shown that the more NCI and NGO are minimized, the more efficient the circuit design is improved [7] It was shown in [8,9,10] that the decrease in energy dissipation in the form of heat is proportional to the minimization of the NGO which shows the great importance of these criteria. The third section presents a literature review of the recent designs proposed related to each study the design of the converter from decimal to BCD encoder and the reversible binary counter while showing the performance criteria of each, for the first study we have six proposals designs and for the second one we have three.

Performance Criteria

HNG Gate

TFG Gate

Fredkin Gate FRG

HNFG Gate

LITERATURE REVIEW

OUR PROPOSED DESIGNS

RESULTS AND DISCUSSION

CONCLUSION