Design Of Coprocessor Research Articles

Design and Implementation of a Deep Convolutional Neural Networks Hardware Accelerator

In a wide variety of cognitive tasks, deep Convolutionary neural networks have recently demonstrated very high precision, and because of this, researchers have attracted considerable attention. Dedicated hardware semiconductors are crucial to improving their efficiency, given the enormous computation complexity of CNNs. The FPGA’s energy usage, computational strength and resilience make it a good tool for CNN additional hardware. This article suggests a coprocessor design with energy-efficient deep convolution neural networks for multi-object detection applications image processing and analysis algorithms. It can support both Convolutionary layers and fully linked layers to speed up various mobile deep learning algorithms. Also, it facilitates optimal and batches normalization activities through a separate arrangement of the pooling module. Besides, in this coprocessor, a reconfigurable activation function module serving four nonlinear functions is also realized. To draw out their connections and distinctions, we group the works into many groups. This paper is useful for artificially intelligent, hardware engineering and machine design experts, making it ideal for smart devices.

A Compact Coprocessor for the Elliptic Curve Point Multiplication over Gaussian Integers

This work presents a new concept to implement the elliptic curve point multiplication (PM). This computation is based on a new modular arithmetic over Gaussian integer fields. Gaussian integers are a subset of the complex numbers such that the real and imaginary parts are integers. Since Gaussian integer fields are isomorphic to prime fields, this arithmetic is suitable for many elliptic curves. Representing the key by a Gaussian integer expansion is beneficial to reduce the computational complexity and the memory requirements of secure hardware implementations, which are robust against attacks. Furthermore, an area-efficient coprocessor design is proposed with an arithmetic unit that enables Montgomery modular arithmetic over Gaussian integers. The proposed architecture and the new arithmetic provide high flexibility, i.e., binary and non-binary key expansions as well as protected and unprotected PM calculations are supported. The proposed coprocessor is a competitive solution for a compact ECC processor suitable for applications in small embedded systems.

Design and Implementation of a Reconfigurable Cryptographic Coprocessor with Multiple Side-Channel Attacks Countermeasures

Nowadays, countermeasures against side-channel attack (SCA) have become necessary in hardware security. And the need for supporting multiple crypto algorithms on a chip is increasing. We propose a reconfigurable crypto coprocessor, which not only supports multiple crypto algorithms, but also provides multiple effective SCA countermeasures of SPA, DPA and EMA, by making use of its own reconfigurable features other than using extra resources. The countermeasure methods include several global and encryption flow related countermeasures, which can also be reconfigured along with the circuit function. This coprocessor is a coarse-grained reconfigurable architecture composed of several reconfigurable modules, such as logic arithmetic, shift, modular ADD/Substrate, permutation, S-box and modular multiplication units, all of which are reconfigurable. This reconfigurable cryptographic coprocessor is integrated into a system-on chip with a 32-bit CPU and fabricated in 0.18 m CMOS process with 1.8[Formula: see text]V supply and 100 MHz maximum frequency. Experimental results show that it can successfully resist SPA and DPA with one million power traces. As for EMA, if we use full countermeasures, it can resist EMA with up to 1.2 million electromagnetic traces without revealing the right subkey. Thus, this reconfigurable coprocessor can provide a good solution for both supporting multiple algorithms and providing SCA resistance, with no frequency influence, neglectable area overhead and small power overhead.

Design of Arithmetic and Logic Coprocessor based on Logarithmic Number System

3D Graphical computing requires more complicated operations such as multiplication , division, square root, power etc., that are computed more faster than conventional method by means of using logarithmic number system (LNS).The proposed implementation is supported in a new set of linear equations, which allows calculating the approximation of the logarithm and antilogarithm binary functions. This design deals with study of logarithmic number system and implementation of an arithmetic and logic unit based on the logarithmic number system.

Design of Parallel Architecture Co-Processor for Particle Swarm Optimization Algorithm

The direct implementation of parallel particle swarm optimization algorithm on Field Programmable Gate Array (FPGA) is presented in this paper. In the proposed design, the particle unit architecture is independent of fitness unit and hence the particle unit is reusable and flexible for different fitness function. The parallel co-processor implementation of each particle accelerates the execution speed and reduces the operating power as compared to the software execution of the design on a general purpose processor. The proposed implementation reduces the number of registers by 2.76% and the number of look-up-tables by 0.62% on average.

Колоночный сопроцессор баз данных для кластерных вычислительных систем

The paper is devoted to the design and implementation issues of columnar coprocessor for RDBMS. Columnar coprocessor (CCOP) is developed on the base of columnar data storage mod-el. It is designed for large computing cluster systems. CCOP can utilize CPUs as well as manycore coprocessors MIC. CCOP maintains the columnar indices with surrogate keys stored in distribut-ed main memory. The partitioning is performed on the base of domain-interval model. For the data warehouse workload, CCOP demonstrates performance much higher than row-stores do.

Design and Implementation of Lossless Data Compression Coprocessor using FPGA

Design and Implementation of Lossless Data Compression Coprocessor using FPGA

Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese

Design of co-processor for real-time HMM-based text-to-speech on hardware system applied to Vietnamese

A Real-Time Sequence Detection Algorithm for Floating Point Unit Design

Sequence detection is used in many algorithms and applications. Sequences are different depending on different demands. In the process of floating-point CORDIC coprocessor design,data are need to change from floating point format to fixed point format. This process is necessary to detect the number of consecutive zeros. We design the leading-zero-counting algorithm to achieve this function, and this conversion process is completed in a very fixed short time, to ensure the needs of the floating point CORDIC coprocessor.

Design and Implement of High Performance Crypto Coprocessor

Design and Implement of High Performance Crypto Coprocessor

BIT-PARALLEL COPROCESSOR FOR STANDARD ECC-$GF(2^m)$ ON FPGA

This paper presents the design of a high-speed coprocessor for Elliptic Curve Cryptography over binary Galois Field (ECC-GF (2)). The purpose of our coprocessor is to accelerate the scalar multiplication performed over elliptic curve points represented by affine coordinates in polynomial basis. Our method consists of using elliptic curve parameters over GF (2163) in accordance Received: April 7, 2013 c © 2013 Academic Publications Correspondence author 242 M.A. Dias, M.R.A. Gouveia, J.R. de Oliveira, I.B. Munoz with international security requirements to implement a bit-parallel coprocessor on field-programmable gate-array (FPGA). Our coprocessor performs modular inversion by using a process based on the Stein’s algorithm. Results are presented and compared to results of other related works. We conclude that our coprocessor is suitable for comparing with any other ECC-hardware proposal, since its speed is comparable to projective coordinate designs. AMS Subject Classification: 14H52, 94A60, 97P60

Design and implementation of a realtime co-processor for denoising Fiber Optic Gyroscope signal

Abstract The amount of noise present in the Fiber Optic Gyroscope (FOG) signal limits its applications and has a negative impact on navigation system. Existing algorithms such as Discrete Wavelet Transform (DWT), Kalman Filter (KF) denoise the FOG signal under static environment, however denoising fails in dynamic environment. Therefore in this paper an Adaptive Moving Average Dual Mode Kalman Filter (AMADMKF) is developed for denoising the FOG signal under both the static and dynamic environments. Performance of the proposed algorithm is compared with DWT and KF techniques. Further, a hardware Intellectual Property (IP) of the algorithm is developed for System on Chip (SoC) implementation using Xilinx Virtex-5 Field Programmable Gate Array (Virtex-5FX70T-1136). The developed IP is interfaced as a Co-processor/ Auxiliary Processing Unit (APU) with the PowerPC (PPC440) embedded processor of the FPGA. It is proved that the proposed system is an efficient solution for denoising the FOG signal in real-time environment. Hardware acceleration of developed Co-processor is 65× with respect to its equivalent software implementation of AMADMKF algorithm in the PPC440 embedded processor.

A co-processor design to accelerate sequential monocular SLAM EKF process

Extended Kalman Filter (EKF) is a non-linear state estimation technique which is used to produce values that close to the true value when given with measurement containing noise and other inaccuracies. In Monocular Simultaneous Localization and Mapping (SLAM), EKF is used to estimate position and motion information. In this paper, Monocular SLAM software implementation on a general purpose computer is studied to find the most time consuming part of the estimation program. The analysis concentrates on the Monocular SLAM EKF estimation process which involves prediction, measurement prediction, matching and update. For this purpose, a form of dynamic programming analysis tool called software profiling is utilized to determine which section of the estimation program demands the highest processing time. Based on the analysis, it is found that EKF “matching” process contribute to the highest computation time. The reason behind the time-consuming process is because for every predicted feature in the matching stage, the acceptance region and their cross correlation have to be calculated. In a typical general purpose computer software implementation, the processing is limited to sequences of operations (i.e. sequential processing). Such implementation will delay the next process until the prior process completed. However, further analysis conducted in this paper shows that each feature does not depend on the prior process and can be processed individually. This would allow several features to be processed simultaneously to improve the execution speed. Therefore, an FPGA pipelined and parallel processing architecture is proposed.

Design of High Speed Reconfigurable Coprocessor for Multiplier/Adder and Subtractions Operations

Design of High Speed Reconfigurable Coprocessor for Multiplier/Adder and Subtractions Operations

Line-by-Line Computation of Atmospheric Infrared Spectra With Field Programmable Gate Arrays

Radiative transfer modelling of high resolution infrared (or microwave) spectra still represents a major challenge for the processing of atmospheric remote sensing data despite significant advances in the numerical techniques utilized in line-by-line modelling by, e.g., optimized Voigt function algorithms or multigrid approaches. Special purpose computing hardware such as Field Programmable Gate Arrays (FPGAs) can be used to cope with the dramatic increase of data quality and quantity. Utilizing a highly optimized implementation of an uniform rational function approximation of the Voigt function, the molecular absorption cross section computation-representing the most compute intensive part of radiative transfer codes-has been realized on FPGA. Design and implementation of the FPGA coprocessor is presented along with first performance tests and an outlook for the ongoing further development.

Design of a Reconfigurable Coprocessor for Double Precision Floating Point Matrix Algorithms

Double precision floating point matrix operations are wildly used in a variety of engineering and scientific computing applications. However, it’s inefficient to achieve these operations using software approaches on general purpose processors. In order to reduce the processing time and satisfy the real-time demand, a reconfigurable coprocessor for double precision floating point matrix algorithms is proposed in this paper. The coprocessor is embedded in a Multi-Processor System on Chip (MPSoC), cooperates with an ARM core and a DSP core for high-performance control and calculation. One algorithm in GPS applications is taken for example to illustrate the efficiency of the coprocessor proposed in this paper. The experiment result shows that the coprocessor can achieve speedup a factor of 50 for the quaternion algorithm of attitude solution in inertial navigation application compare with software execution time of a TI C6713 DSP. The coprocessor is implemented in SMIC 0.13μm CMOS technology, the synthesis time delay is 9.75ns, and the power consumption is 63.69 mW when it works at 100MHz.

Design of a Low-Power Coprocessor for Mid-Size Vocabulary Speech Recognition Systems

Speech recognition systems have gained popularity in consumer electronics. This paper presents a custom-designed coprocessor for output probability calculation (OPC), which is the most computation-intensive processing step in continuous hidden Markov model (CHMM)-based speech recognition algorithms. To save hardware resource and reduce power consumption, a polynomial addition-based method is used to compute add-log instead of the traditional look-up table-based method. In addition, the optimal tradeoff between speech processing delay, energy consumption, and hardware resources is explored for the coprocessor. The proposed coprocessor has been implemented and tested in Xilinx Spartan-3A DSP XC3SD3400A, and also validated using the standard-cell-based approach in IBM 0.13 μm technology. To implement an entire speech recognition system, SAMSUNG S3C44b0X (containing an ARM7) is used as the micro-controller to execute the rest of speech processing. Tested with a 358-state 3-mixture 27-feature 800-word HMM, S3C44b0X operates at 40 MHz and coprocessor at 10 MHz to meet the real-time requirement, and the recognition accuracy is 95.2%. Power consumption of the micro-controller is 10 mW, and that of the coprocessor 15.2 mW. The overall speech recognition system achieves the lowest energy consumption per word recognition among many reported designs. Experiment and analysis show that the speech recognition system based on the proposed coprocessor is especially suitable for mid-size vocabulary (100-1000 words) recognition tasks.

The Design of Coprocessor for Portable Electronic Devices Based on Tightly Coupled Structure

In this paper, we introduced a kind of low cost security coprocessor architecture for portable electronic devices, whose core is the reconfigurable, scalable and tightly coupled security coprocessor architecture. The coprocessor integrates the resources of system effectively, and greatly reduces the power consumption as well as the area of the chip in the case of ensuring the data throughput needed of portable electronic devices.

Explicit design of FPGA-based coprocessors for short-range force computations in molecular dynamics simulations

FPGA-based acceleration of molecular dynamics simulations (MD) has been the subject of several recent studies. The short-range force computation, which dominates the execution time, is the primary focus. Here we combine: a high level of FPGA-specific design including cell-lists, systematically determined interpolation and precision, handling of exclusion, and support for MD simulations of up to 256 K particles. The target system consists of a standard PC with a 2004-era COTS FPGA board. There are several innovations: new microarchitectures for several major components, including the cell-list processor and the off-chip memory controller; and a novel arithmetic mode. Extensive experimentation was required to optimize precision, interpolation order, interpolation mode, table sizes, and simulation quality. We obtain a substantial speed-up over a highly tuned production MD code.

Hardware implementation of a stereo co-processor in a medium-scale field programmable gate array

The design of a hardware co-processor for stereo depth detection, based on a parallel implementation of the Sum of Absolute Differences algorithm, is presented. Model-based designs are followed, and a parameterisable open source VHDL library component appropriate for integration within a system-on-a-programmable chip is created. We target a field programmable gate array board featuring external memory and other peripheral components and implement the control path with a Nios II embedded processor clocked at 100 MHz. The hardware co-processor produces dense 8-bit disparity maps of 320×240 pixels at a rate of 25 Mpixels/s and can expand the disparity range from 32 to 64 pixels with appropriate memory techniques. Essential resources can be as low as 16 000 logic elements, whereas by migrating to more complex devices the design can easily grow to support better results.