Design and Implementation of a Deep Convolutional Neural Networks Hardware Accelerator

Abstract

In a wide variety of cognitive tasks, deep Convolutionary neural networks have recently demonstrated very high precision, and because of this, researchers have attracted considerable attention. Dedicated hardware semiconductors are crucial to improving their efficiency, given the enormous computation complexity of CNNs. The FPGA’s energy usage, computational strength and resilience make it a good tool for CNN additional hardware. This article suggests a coprocessor design with energy-efficient deep convolution neural networks for multi-object detection applications image processing and analysis algorithms. It can support both Convolutionary layers and fully linked layers to speed up various mobile deep learning algorithms. Also, it facilitates optimal and batches normalization activities through a separate arrangement of the pooling module. Besides, in this coprocessor, a reconfigurable activation function module serving four nonlinear functions is also realized. To draw out their connections and distinctions, we group the works into many groups. This paper is useful for artificially intelligent, hardware engineering and machine design experts, making it ideal for smart devices.