Charge Pump Design Research Articles

Multistage Charge Pump Design Methodology for Zero-Crossing-Based Amplifiers

Multistage Charge Pump Design Methodology for Zero-Crossing-Based Amplifiers

Liftoff of a soft-actuated micro-aerial-robot powered by triboelectric nanogenerators

Aerial insects can nimbly navigate in cluttered natural environments while they interact with delicate objects such as flowers and leaves. To achieve insect-like agility and robustness, power dense dielectric elastomer actuators (DEAs) have been developed for driving sub-gram micro-aerial-vehicles (MAVs). However, despite exhibiting muscle-like bandwidth and resilience, DEAs require a high driving voltage in the range of 1 – 2 kilovolts. This requirement poses substantial challenges for developing compact boost electronics and energy sources, which prohibit power autonomous operations of soft-actuated sub-gram MAVs. Here, we develop a compact and high power triboelectric nanogenerator (TENG) that can effectively charge a high-voltage DEA and enable the liftoff of a soft-actuated MAV. We propose an In-plane Charge Pump (ICP) design that can deliver over 1500 V and 110 mW without requiring a secondary charge pump or magnetic circuit components such as inductors or transformers. Compared to conventional free-standing mode TENGs, our ICP design shows a 280 % and 920 % increase in voltage and energy generation, respectively. When this TENG powers a DEA-driven MAV, the 160 mg robot achieves liftoff with a lift-to-weight ratio of 1.75. This result highlights the potential of powering high-voltage microrobots with energy-harvesting devices.

In-depth Multi-Objective charge pump design space exploration towards the automatic synthesis of power management units

The inclusion of automation mechanisms in the intricate design of power management units (PMUs) is long pursued in industry. This paper addresses a mixed-signal design flow whose purpose is to automatically produce, from the system-level to the ready-for-tape-out layout, complex PMUs when given a set of specifications. Particularly, in that flow, at the IP level, the proper analysis of the design tradeoffs is tedious and impractical, as a large amount of conflicting performance figures obtained from transient analysis for typical and multiple process/temperature corners, must be considered simultaneously. Therefore, it is common for the design cycle of a single integrated charge pump required in a state-of-the-art PMU to surpass a full month, depending on the intended technology, devices’ types and operation voltages. Additionally, by the end of this process, circuit designers often end up with a limited vision of the attainable performances. However, due to the recent improvements in computational power of modern workstations, optimization-based techniques with expensive evaluation mechanisms are now perceived as a potential solution to pursue optimal sizing and layout. Therefore, an academic electronic design automation tool is adapted and applied to explore the performance boundaries of a charge pump in a 180-nm technology node and determine the optimal tradeoffs between performance and the, severely constrained, layout area. In the last step, a worst-case corner optimization on a 45- and 99- dimensional design and performance spaces, respectively, derived from 9 time-consuming transient analysis of each candidate solution, produced 35 design solutions that provide a thorough analysis between worst-case efficiency, voltage drop, and rise and fall times, impossible to perform in the manual design. The obtained insights on the design space were used to speed-up the process of devising a solution for tape-out.

An Integrated Charge Pump for Phase-Locked Loop Applications in Harsh Environments

Among all the functions that electronics currently perform, clock synthesis has a backbone role. Charge pump phase-locked loops (CP-PLL) are widely used to accomplish clock synthesis thanks to their versatility. One of the most critical parts of CP-PLLs is the charge pump, which greatly influences the system’s performance. Even though several high-performance charge pumps have been proposed in the past, with the quick spread of electronics in all the engineering fields, the design of such electronic devices has encountered several additional challenges dictated by external environmental conditions. Examples of these engineering sectors are space, aerospace, industrial, and automotive applications, where the charge pump has to face high environmental temperatures and radiation effects. As a consequence, its design and experimental characterization have to be performed to ensure reliability when operating in harsh conditions. However, to the best of the authors’ knowledge, no works in the literature have ever presented a complete charge pump design and characterization in such harsh environments. Therefore, to fill this gap, this paper presents a charge pump for PLL applications specifically designed to reach operating temperatures up to 200 °C and total ionizing dose levels up to 100 Mrad. All design choices have been experimentally verified and are discussed throughout the paper in detail. With the proposed design, we obtained an output current variation of less than 8% at 200 °C and less than 2.5% at 100 Mrad. As opposed to the CPs that can be found in the literature, these results were measured on silicon. The performed measurements confirm that the current variation at 200 °C is better than that of the state-of-the-art CPs operating at lower temperatures, which, moreover, were only simulated.

A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL application

A high-speed MCML charge pump design at 10 GHz frequency in 45 nm CMOS technology for PLL application

Modeling and Design of Cold-Start Charge Pumps for Photovoltaic Energy Harvesters

Modeling and Design of Cold-Start Charge Pumps for Photovoltaic Energy Harvesters

One-Dimensional Maximum Power Point Tracking Design of Switched-Capacitor Charge Pumps for Thermoelectric Energy Harvesting

This paper proposes a one-dimensional (1D) maximum power point tracking (MPPT) design which only requires measurement of one parameter (the input voltage of a switched-capacitor charge pump) for calibrating a power converter including the charge pump and thermoelectric generator. The frequency of the clock to drive the charge pump is designed to minimize the circuit area of the entire charge pump circuit for generating a target output current at a specific output voltage. The ratio of the capacitance value of each boosting capacitor (C) to the size of the switching MOSFET can be determined to maximize the transferring current at the same time. When a thermoelectric generator (TEG) is given, its output impedance is determined. Its open-circuit voltage varies with the temperature difference between two plates of the TEG. MPPT maximizes the output power of the charge pump even when the temperature difference varies. It was indicated that the number of stages of charge pump (N) needs to increase when the temperature difference lowers, whereas C needs to decrease inversely proportional to N, meaning that the C–N product should be kept unchanged for MPPT. Demonstration of the circuit design was conducted in 65 nm CMOS, and the measured results validated the concept of the 1D MPPT.

Analysis and Design of High-Efficiency Charge Pumps With Improved Current Driving Capability Using Gate Voltage Boosting Technique

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 1.24\times $ </tex-math></inline-formula> more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%.

A 0.25–0.4-V, Sub-0.11-mW/GHz, 0.15–1.6-GHz PLL Using an Offset Dual-Path Architecture With Dynamic Charge Pumps

This article presents an ultra-low-voltage phase-locked loop (ULVPLL) with the minimum supply voltage at 0.25 V. The offset dual-path loop architecture is proposed to relax the charge pump (CP) current matching requirement. Thus, no current mismatch suppression technique is required. This significantly mitigates the CP design challenges at such low supply voltage. In the two proposed dynamic CPs (DCPs), all the current sources, current mirrors, and op amps in the prior CPs are eliminated. Hence, the CP voltage headroom requirement is relaxed to make the DCP be suitable for sub-0.3-V operation; meanwhile, the CP power consumption and circuit design complexity are simultaneously reduced. Implemented in 40-nm CMOS with core area of 0.00873 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the 0.15-1.6-GHz ULVPLL is capable of operation under a 0.25-0.4-V supply voltage. The power efficiency is 0.106 mW/GHz from 1.6-GHz output (at 0.4-V supply) and 0.048 mW/GHz from 0.2 GHz (at 0.25-V supply). Measured spur level is -58.3 dBc at 100-MHz offset from 1.6-GHz output (at 0.4-V supply) and -48.5 dBc at 12.5-MHz offset from 200-MHz output (at 0.25-V supply).

Design of a Novel Current Mode Charge Pump for Very-Low-Voltage Applications in 130 nm SOI-BCD Technology

A novel charge pump with current mode control suitable to work under a very-low-voltage supply is proposed in this paper. The proposed charge pump consists of two sections. The first section is a power switches stage which consists of seven cascaded DEPMOS power switches. The second section is a low voltage stage which consists of a Low Voltage Level Shifter, Current Mode control, Follower Amplifier, Error Amplifier, Soft Start Comparator, and Skip mode &amp; Over Voltage Comparator. The charge pump has been designed, simulated, and layout in Cadence using TSMC 130 nm SOI technology with LDMOS transistors, which have very low on-resistance. The input range of the charge pump is 2.7– 4.4 V, and it can supply up to 100 mA load current. The maximum efficiency is 90%, and the chip area is only 0.597 mm².

Modeling, Design, and Testing of a Linear Electric-Hydraulic Conversion Machine for Electrification of Off-Highway Vehicles

Electrification and hybridization of off-highway vehicles have the potential to yield significant fuel savings and air emissions improvements. However, developing the required components to electrify these systems is an extremely challenging task due to high force and power density requirements and highly variable drive cycles. This article investigates a new approach to off-highway vehicle electrification based around a linear piston pump integrated into a linear actuator. The article first reviews linear actuator machine topologies within the context of the charge pump application requirements. A tubular machine topology is optimized for integration with a hydraulic pump and experimentally validated using a prototype machine. A multiphysics simulation framework is developed to simulate the entire charge pump design with a position regulator. An optimized design is proposed with an oscillation frequency of 132 Hz and a total system efficiency (pump and motor) calculated to be 81.3% at full load.

High-temperature LTCC assembly and design of SiC BJT-based negative charge pump

ABSTRACT This paper describes the negative charge pump design in state-of-the-art SiC BJT technology along with its assembly on the LTCC module for extremely high-temperature applications. Kiln thermal oven is used to test the system at 500°C and evaluate the system’s high-temperature performance. The charge pump design is separated into two sections: a diode-connected BJT charge pump and a cross-coupled RC oscillator. Commercially available NHT dielectric capacitors (390 pF) are used for both circuit sections. The designed LTCC module used DuPont™ 9k7 dielectric with gold metallization for routing traces. The oscillator output frequency varied from 35.7 kHz to 125 kHz across temperature for a fixed supply voltage of 11 V.

Design Topologies of a CMOS Charge Pump Circuit for Low Power Applications

Applications such as non-volatile memories (NVM), radio frequency identification (RFID), high voltage generators, switched capacitor circuits, operational amplifiers, voltage regulators, and DC–DC converters employ charge pump (CP) circuits as they can generate a higher output voltage from the very low supply voltage. Besides, continuous power supply reduction, low implementation cost, and high efficiency can be managed using CP circuits in low-power applications in the complementary metal-oxide-semiconductor (CMOS) process. This study aims to figure out the most widely used CP design topologies for embedded systems on the chip (SoC). Design methods have evolved from diode-connected structures to dynamic clock voltage scaling charge pumps have been discussed in this research. Based on the different architecture, operating principles and optimization techniques with their advantages and disadvantages have compared with the final output. Researchers mainly focused on designing the charge pump topologies based on input/output voltage, pumping efficiency, power dissipation, charge transfer capability, design complexity, pumping capacitor, clock frequencies with a minimum load balance, etc. Finally, this review study summarizes with the discussion on the outline of appropriate schemes and recommendations to future researchers in selecting the most suitable CP design methods for low power applications.

High-Efficiency High Voltage Hybrid Charge Pump Design With an Improved Chip Area

A hybrid charge pump was developed in a 0.13- μm Bipolar-CMOS-DMOS (BCD) process which utilised high drain-source voltage MOS devices and low-voltage integrated metal-insulator-metal (MIM) capacitors. The design consisted of a zero-reversion loss cross-coupled stage and a new self-biased serial-parallel charge pump design. The latter has been shown to have an area reduction of 60% in comparison to a Schottky diode-based Dickson charge pump operating at the same frequency. Post-layout simulations were carried out which demonstrated a peak efficiency of 38% at the output voltage of 18.5 V; the maximum specified output voltage of 27 V was also achieved. A standalone serial-parallel charge pump was shown to have a better transient response and a flatter efficiency curve; these are preferable for time-sensitive applications with a requirement of a broader range of output currents. These findings have significant implications for reducing the total area of implantable high-voltage devices without sacrificing charge pump efficiency or maximum output voltage.

Design of a dual-input cross-connected charge pump utilizing scavenged energy

This paper presents a novel dual-input cross-connected charge pump utilizing scavenged energy. The proposed converter has two input sources: a battery input and a scavenged energy input. Unlike existing charge pumps, the proposed converter alleviates the energy consumed in a battery source by utilizing the scavenged energy. Therefore, the proposed converter can extend the lifetime of a battery source. Furthermore, the cross-connected structure offers not only higher voltage gain but also faster response speed than existing charge pumps. Through theoretical analysis and simulation program with integrated circuit emphasis (SPICE) simulation, the proposed converter demonstrates high power efficiency and high output voltage, where the proposed converter is compared with series–parallel converter, traditional charge pump, and Fibonacci converter. Concretely, about 90% power efficiency can be achieved by the proposed converter when the output power is 15 μW, and the settling time is less than 19 μS when the output load is 500kΩ. Furthermore, the feasibility of the proposed converter is confirmed by breadboard experiments, where the experimental circuit is built with commercially available ICs.

Integer‐ N charge pump phase locked loop for 2.4 GHz application with a novel design of phase frequency detector

In this article, a novel design is presented, for an Integer- N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage-controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near-zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three-stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power.

Cross-Coupled Charge Pump Synthesis Based on Full Transistor-Level

This paper presents utility for the design of the cross-coupled charge pump, which is used for supplying peripherals with low current consumption on the chip, as the EEPROM or FLASH memories. The article summarizes the knowledge in the field of the theoretical and practical analysis of the cross-coupled charge pump (design relationships and their connection with the pump parameters, as the threshold voltage, power supply voltage, clock signal frequency, etc.) that are applicated in the design algorithm. Optimal MOSFETs sizes (W, L) were find based on the construct of the time response characteristics of the pump sub-block and finding of the maximal voltage increase in the active interval of the clock signal and minimizing of the pump losses, as the switch reverse current, inverter cross current, etc. Synthesis process includes the design of the pump functional blocks with dominant real properties, which are described based on BSIM equations for long channel MOSFET. The pump stage complex model is applicated for estimation of the number of pump stages via state-space model description and using of the interpolation polynomial functions in the algorithm. It involves the construction of the time response characteristic due to the state variables and prediction of the number of the pump stages for the next cycle based on the previous data. Optimization of the pump area is based on the minimizing of the main capacitor in each of the pump stages (number of the pump stages must be increased to obtain the desired output voltage value.) Access is designed to stress the maximum pump voltage efficiency. The whole procedure is summarized in the practical example, in which the solution is shown both in terms of maximal voltage efficiency and the optimal pump area on a chip with respect to the clock signal frequency. Added functions of the design environment are explained, inclusive of the designed pump netlist generating for professional design environment Mentor Graphics including the real models of components that are available in library MGC Design Kit. The procedure gives designer credible results without long timeconsuming optimization process. In addition, the complex model allows the inclusion effects of higher-levels.

An Efficient and Novel Design of Loop Filter, Charge Pump and VCO for PLL Using CMOS Technology

This article presents an occasional energy charge pump, low pass filter and voltage supervised generator for little energy section loop. PLL are generally used for synchronization and regulate of grid- associated power electronic techniques. The article enfolds the whole circuit figure of circle filter, charge pump and voltage restrict oscillator through 1.8v energy stock. This kind uses 0.18um CMOS technology. In recent times, voltage restricted oscillator are employed for phase lock loop. A great viable loop-bandwidth plan method, derivative from a distinct -time PLL model, additional complements the jitter attributes of a PLL previously somewhat evolved via optimizing precisecircuit elements. The expressed system no longer simplest guesstimates the timing jitter of a PLL, but additionally attains the most reliable bandwidth reducing the at the whole PLL jitter.

An Efficient and Novel Design of Loop Filter, Charge Pump and VCO for PLL Using CMOS Technology

This article presents an occasional energy charge pump, low pass filter and voltage supervised generator for little energy section loop. PLL are generally used for synchronization and regulate of grid- associated power electronic techniques. The article enfolds the whole circuit figure of circle filter, charge pump and voltage restrict oscillator through 1.8v energy stock. This kind uses 0.18um CMOS technology. In recent times, voltage restricted oscillator are employed for phase lock loop. A great viable loop-bandwidth plan method, derivative from a distinct -time PLL model, additional complements the jitter attributes of a PLL previously somewhat evolved via optimizing precisecircuit elements. The expressed system no longer simplest guesstimates the timing jitter of a PLL, but additionally attains the most reliable bandwidth reducing the at the whole PLL jitter.

Design of a cross-connected charge pump for energy harvesting systems

For energy harvesting systems, a novel charge pump with cross-connected structure is proposed in this paper. Owing to the cross-connected structure, the proposed charge pump can offer the output voltage to the output load at every phase. Furthermore, the proposed charge pump can reduce the number of circuit stages from the conventional charge pump. For above-mentioned reasons, the proposed charge pump can realize not only smaller internal resistance but also smaller output capacitance than the conventional charge pump. The theoretical analysis and simulation program with integrated circuit emphasis (SPICE) simulation demonstrate that the proposed charge pump outperforms the conventional charge pump in the point of power efficiency and circuit speed.